飲料自動售賣機設計含開題及8張CAD圖,飲料,自動,售賣,設計,開題,cad 譯文報告用紙 AT89S51是美國ATMEL公司生產的一款高性能、低功耗的CMOS8位單片機，片內的Flash只讀程序存儲器容量為4 bytes，器件采用ATMEL公司的高密度、非易失性存儲技術生產，能夠兼容8051指令系統(tǒng)和引腳。它匯集Flash程序存儲器既可在線編程又能用傳統(tǒng)的方式編程及通用8位微處理器于單片機芯片中。ATMEL公司功能強大、價格低廉的AT89S51單片機可為您提供許多高性價比的應用場合，可靈活應用于各種控制領域。 主要性能參數(shù)： u 與MCS-51產品指令完全兼容 u 4K字節(jié)在線系統(tǒng)編程（ISP）Flash閃存 u 1000次擦寫周期 u 4.0-5.5V的工作電壓范圍 u 全靜態(tài)工作模式：0HZ-33MHZ u 三級程序加密鎖 u 128 x 8字節(jié)內部RAM u 32個可編程I/O接口 u 2個16位置定時/計數(shù)器 u 6個中斷源 u 全雙工串行UART通道 u 低功耗空閑和掉電模式 u 中斷可從空閑模式喚醒系統(tǒng) u 看門狗（WRT）及雙數(shù)據指針 u 掉電標識和快速編輯特性 u 靈活的在線系統(tǒng)編程 功能特性概述： AT89S51提供以下標準功能：4K字節(jié)Flash閃速存儲器，128字節(jié)內部RAM，32個I/O口線，看門狗（WTR），兩個數(shù)據指針，兩個16位定時/計數(shù)器，一個5向量兩級中斷結構，一個全雙工串行通信口，片內振蕩器及時鐘電路。同時AT89S51可降至0HZ的靜態(tài)邏輯操作，并支持兩種軟件可選的節(jié)電工作模式?？臻e方式停止CPU的運作，但允許RAM、定時/計數(shù)器、串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的內容，但振蕩器停止工作并禁止其他一切部件工作，直到下一個硬件復位。 引腳功能說明： VCC：電源電壓 GND：接地端 P0口：P0口是一組8位開路型漏極雙向I/O口。作為輸出口用時，每位能驅動8個TTL邏輯門電路，對端口寫 “1”可作為高阻抗輸入端用。 在訪問外部數(shù)據存儲器或者程序存儲器時，這組端口分時轉換地址的低8位和數(shù)據總線復用，訪問期間內部上拉電阻被激活。 在Flash編程時P0口接收指令字節(jié)，而在程序校驗時輸出指令字節(jié)并要求外接上拉電阻。 P1口：P1口時一個帶內部上拉電阻的8位雙向I/O口，P1的輸出緩沖級（吸收或輸出電流）4個TTL邏輯門電路。對端口寫“1”，通過內部上拉電阻把端口拉到高電平，此時可以作為輸入口。因為存在內部上拉電阻，P1口作為輸入口使用時，某個引腳被外部信號拉到低電平會輸出一個電流IIL_ Flash編程和編程校驗期間，P1接收低8位地址。 P2口：P2時一個帶內部上拉電阻的8位雙向I/O口，P2的輸出緩沖級可驅動（吸收或輸出電流）4個TTL邏輯門電路。對端口寫“1”，通過內部的上拉電阻，某個引腳被外部信號拉低時會輸出一個電路。 在訪問外部程序存儲器或者16位地址的外部數(shù)據存儲器（例如執(zhí)行MOVX @DPTR指令）時，P2口送出高8位地址數(shù)據。在訪問8位地址的外部數(shù)據存儲器（如執(zhí)行MOVX @Rｉ指令）時，P2口線上的內容（也即特殊功能寄存器（SFR）區(qū)中P2寄存器的內容），在整個訪問期間不會改變。 Flash編程或者校驗時，P2也接收高位地址和其他控制信號。 P3口：P3口時一組帶內部上拉電阻的8位雙向I/O口。P3口輸出緩沖級可驅動（吸收或輸出電流）4個TTL邏輯門電路。對P3口寫入“1”時，它們被內部上拉電阻拉高并可以作為輸入端口。作為輸入端時，被外部信號拉低的P3口將用上拉電阻輸出電流IIL。 P3口除了作為一般的I/O口線外，更重要的用途時它的第二功能，如下表所示： P3口還接收一些用于Flash閃速存儲器編程和程序校驗的控制信號。 RST：復位輸入。當振蕩器工作時，RST引腳出現(xiàn)兩個機器周期以上的高電平將使得單片機復位。WDT溢出將使得該引腳輸出高電平，設置SFR AUXR 的DISRTO位（地址8EH）可打開或者關閉該功能。DISRTO位缺省為RESET輸出高電平打開狀態(tài)。 ALE/：當訪問外部程序存儲器或者數(shù)據存儲器時，ALE（地址鎖存允許）輸出脈沖用于鎖存地址的低8位字節(jié)。即使不訪問外部存儲器，ALE仍然以時鐘振蕩頻率的1/6輸出固定的正脈沖信號，因此它可對外輸出時鐘或者用于定時目的。要注意的是，每當訪問外部數(shù)據存儲器時將跳過一個ALE脈沖。 對Flash存儲器編程期間，該引腳還用于輸入編程脈沖（）。 如有必要，可通過對特殊功能寄存器（SFR）區(qū)中的8EH單元的D0位置位，可禁止ALE操作。該位置位后只有MOVX和MOVC指令ALE才會被激活。此外，該引腳會被稍微拉高，單元執(zhí)行外部程序時，應設置ALE無效。 :程序存儲允許（）輸出的時外部程序存儲器的讀選通信號，當AT89S51由外部程序存儲器取指令（或者數(shù)據）時，每個機器周期兩次有效，即輸出兩個脈沖。當訪問外部數(shù)據存儲器時，沒有兩次有效的信號。 EA/VPP：外部訪問允許。欲使得CPU僅訪問外部程序存儲器（地址為0000H-FFFFH），EA端必須保持低電平（接地）。需要注意的是，如果加密位LB1被編程，復位時內部會鎖存EA端狀態(tài)。 如果EA端時高電平（接VCC端），CPU則執(zhí)行內部程序存儲器中的指令。 Flash存儲器編程時，該引腳加上+12V的編程電壓VPP。 XTAL1：振蕩器反相放大器及內部時鐘發(fā)生器的輸入端。 XTAL2：振蕩器反相放大器的輸出端。 特殊功能寄存器： 特殊功能寄存器內部空間分布如下表所示： 這些地址并沒有全部占用，沒有占用的地址也不可以使用，讀這些地址將會得到一個不確定的數(shù)值。而寫這些地址單元也將得不到預期的結果。 表1 AT89S51特殊功能寄存器分布圖及復位值 不要用軟件方式訪問這些未定義的單元，這些單元時留作以后產品擴展之用，復位后這些新的位將置為0. 中斷寄存器：各個中斷允許控制位于IE寄存器，5個中斷源的中斷優(yōu)先級控制位位于IP寄存器中。 表2 AUXR輔助寄存器 雙時鐘指針寄存器： 為更加方便地訪問內部和外部數(shù)據存儲器，AT89S51有兩個16位數(shù)據指針寄存器：DP0位于SFR（特殊功能寄存器）區(qū)塊中的地址82H、83H和DP1位于地址84H、85H，當SFR中的位DPS=0選擇DP0，而當DPS=1則選擇DP1。用戶應在訪問相應的數(shù)據指針寄存器前初始化DPS。 電源空閑標志：電源空閑標志(POF)在特殊功能寄存器SFR中PCON的第4位（PCN.4），電源打開時POF置“1”，它可由軟件設置睡眠狀態(tài)并不為復位所影響。 存儲器結構：MCS-51單片機內核采用了程序存儲器和數(shù)據存儲器空間分開的結構，都具有64KB的外部程序和數(shù)據的尋址空間。 程序存儲器：如果EA引腳接地（GND），全部程序均執(zhí)行外部存儲器。在AT89S51中，如果EA接到VCC（電源+），程序首先執(zhí)行地址從0000H-0FFFH（4KB）內部程序存儲器，再執(zhí)行地址為1000H-FFFFH（60KB）的外部程序存儲器。 數(shù)據存儲器：AT89S51有128字節(jié)的內部RAM，這128字節(jié)可利用直接或者間接尋址方式進行訪問，堆棧操作可以利用間接尋址方式進行，128字節(jié)均可設置位堆棧區(qū)空間。 看門狗定時器（WDT）：WDT為了解決CPU程序運行時可能進入混亂或者死循環(huán)而設置，它由一個14Bit計數(shù)器和看門狗復位SFR（WDTRST）構成。外部復位時，WDT默認為關閉狀態(tài)，要打開WDT，用戶必須按順序把01EH和0E1H寫到WDTRST寄存器（SFR地址為0A6H），一旦啟動了WDT，它會隨晶體振蕩器在每個機器周期計數(shù)，除硬件復位或WDT溢出復位外沒有其他方法關閉WDT，當WDT溢出，將使RST引腳輸出高電平的復位脈沖。 使用看門狗（WDT）：打開WDT需按次序寫01EH和0E1H到WDTRST寄存器（SFR的地址為0A6H），當WDT打開后，需要一定的時間寫01EH和0E1H到WDTRST寄存器以避免WDT技術溢出。14位WDT計數(shù)器計數(shù)達到3FFFFH，WDT將溢出并使得器件復位。WDT打開時，它會隨著晶體振蕩器在每個機器周期計數(shù)，這意味著用戶必須在小于每個3FFFH機器周期內復位WDT，也即寫01EH和0E1H到WDTRST寄存器。WDTRST是只寫寄存器，WDT計數(shù)器既不可以讀也不可以寫，當WDT溢出時，通常將使得RST引腳輸出高電平的復位脈沖。復位脈沖持續(xù)時間為98xTOSC，而TOSC=1/FOSC（晶體振蕩頻率）。為使得WDT工作最優(yōu)化，必須在合適的程序代碼時間段周期地復位WDT防止WDT溢出。 掉電和空閑時的WDT：掉電時期，晶體振蕩停止，WDT也停止。掉電模式下，用戶不能再復位WDT。有兩種方法可以退掉掉電模式：硬件復位或通過激活外部中斷。當硬件復位退出電模式時，處理WDT可像通常的上電復位一樣。當由中斷退出掉電模式則有所不同，中斷低電平狀態(tài)持續(xù)到晶體振蕩穩(wěn)定，當中斷電平變?yōu)楦呒错憫袛喾?。位防止中斷誤復位，當器件復位，中斷引腳為低時，WDT并未開始給計數(shù)，直到中斷引腳為高為止。這為在掉電模式下的中斷執(zhí)行中斷服務程序而設置。 為保證WDT在退出掉電模式時極端情況下不溢出，最好在進入掉電模式前復位WDT。 在進入空閑模式前，WDT打開時WDT是否計數(shù)由SFR中的AUXR的WDIDLE位決定IDLE期間（位WDIDLE=0）默認狀態(tài)是繼續(xù)計數(shù)。為防止AT89S51從空閑模式中復位，用戶應周期性設置定時器，重新進入空閑模式。、 當WDIDLE被復位，在空閑模式中WDT將停止計數(shù)，直到從空閑（IDLE）模式中重新開始計數(shù)。 UART一通用異步通信口：AT85S51的UART操作與AT89C51一樣，有關更詳細的資料請參考ATMEL公司的網站（www.atmel.com）,從主頁選擇“products”-----“8051-Architecture Flash Microcontroller”-----“product Overview”。 定時器0和定時器1：AT89S51的定時器0和定時器1操作于ATC51一樣，有關更詳細的資料請參考ATMEL公司的網站（www.atmel.com），從主頁選擇“Products”——“8951-Architecture Flash Microcontroller”——“Product Overview”。 中斷：AT89s51共有5個中斷向量：兩個外部中斷（INT0和INT1），2個定時中斷（Timer0和Timer1）和一個串行中斷。這些中斷如圖1. 這些中斷源各自的禁止和使能位參見特殊功能寄存器的IE。IE也包括總中斷控制位EA，EA清零將關閉所有中斷。 值得注意的時表4中的IE.6和IE.5沒有定義，用戶不用訪問這些位它被保留為以后的AT89產品作為擴展之用。 定時器0和定時器1的中斷標志TF0和TF1，它時定時器溢出時候的S5P2時序周期被置位，該標志保留到下個時序周期。 表4：中斷控制寄存器 圖1：中斷源方框圖 晶體振蕩器的特性： AT89S51中由一個用于構成內部振蕩器的高增益反相放大器，引腳XTAL1和XTAL2分別時該放大器的輸入端和輸出端。這個放大器與作為反饋元件的片外石英晶體或陶瓷振蕩器一起構成自激振蕩器，振蕩電路參見圖5. 外接石英晶體（或陶瓷振蕩器）及電容C1、C2接在放大器的反饋回路中構成并聯(lián)振蕩電路。對外接電容C1、C2雖然沒有十分嚴格的要求，但電容量的大小會輕微影響振蕩頻率的高低、振蕩器工作的穩(wěn)定性、起振的難易程度及溫度的穩(wěn)定性如果使用石英晶體，我們推薦使用30pF+10F，而如果使用陶瓷諧振器建議選擇40pF+10F。 用戶也可以采用外部時鐘。采用外部時鐘的電路如圖5右圖所示。這種情況下，外部時鐘脈沖接到XTAL1端，即內部時鐘發(fā)生器的輸入端，XTAL2懸空。 由于外部時鐘信號時通過一個2分頻觸發(fā)器后作為內部時鐘信號的，所以對外部時鐘信號的占空比沒有特殊要求，但最小高電平持續(xù)時間和最大的低電平持續(xù)時間應符合產品計數(shù)條件的要求。 圖2 晶體接線圖和外接時鐘線路圖： 空閑節(jié)電模式：在空閑工作模式狀態(tài)，CPU保持睡眠狀態(tài)而所有片內的外設仍然保持激活狀態(tài)，這種方式由軟件產生，片內RAM和所有特殊功能寄存器的內容保持不變?？臻e模式可由任何允許的中斷請求或硬件復位終止。 需要注意的是，當由硬件復位來終止空閑模式時，CPU通常是從激活空閑模式那條指令的下一條指令開始繼續(xù)執(zhí)行程序的，要完成內部復位操作，硬件復位脈沖要保持兩個機器周期（24個時鐘周期）有效，在這種情況下，內部禁止CPU訪問片內RAM，而允許訪問其他端口。為了避免在復位結束時可能對端口產生意外寫入，激活空閑模式的那條指令后一條指令不應是一條對端口或外部存儲器的寫入指令。 掉電模式：在掉電模式下，振蕩器停止工作，進如掉電模式的指令時最后一條被執(zhí)行的指令，片內RAM和特殊功能寄存器的內容在終止掉電模式前被凍結。退出掉電模式的方法時硬件復位或由處于使能狀態(tài)的外中斷INT0和INT1激活。復位后將重新定義全部的特殊功能寄存器但不改變RAM中的內容，在Vcc恢復到正常工作電平前，復位應無效，且必須保持一定時間按以使振蕩器重啟并穩(wěn)定工作。 表5 空閑和掉電期間外部引腳狀態(tài)： 程序存儲器的加密：AT89S51可使用對芯片上的3個加密位LB1、LB2、LB3進行編程（P）或不編程（U）來得到如下表所示的功能： 加密位保護功能表： 注：表中的U——表示未編程，P——表示編程 當加密位LB1被編程時，在復位期間，EA端的邏輯電平被采樣并鎖存，如果單片機上電后一直沒有復位，則鎖存其來的初始值時一個隨機數(shù)，且這個隨機數(shù)會一直保存到真正復位為止。為使單片機能正常工作，被鎖存的EA電平值必須與該引腳當前的邏輯電平一致。此外，加密位只能通過整片擦除的方法清除。 Flash閃速存儲器的并行編程：AT89S51單片機內部有4k字節(jié)的可快速編程的Flash存儲陣列。編程方法可通過傳統(tǒng)的EPROM編程器使用高電壓（+12v）和協(xié)調的控制信號進行編程。 AT89S51的代碼是逐一字節(jié)進行編程的。 編程方法：編程前，須按照編程模式表和圖13、圖14所示設置好地址、數(shù)據及控制信號，AT89S51編程方法如下： 1. 在地址線上加上要編程單元的地址信號 2. 在數(shù)據線上加上要寫入的數(shù)據字節(jié) 3. 激活相應的控制信號 4. 將EA/Vpp端加上+12編程電壓。 5. 每對Flash存儲陣列寫入一個字節(jié)或每寫入一個程序加密位，加上一個ALE/編程脈沖。每個字節(jié)寫入周期是自身定時的，大多數(shù)約為50uS。改變編程單元的地址和寫入的數(shù)據，重復1——5步驟，直到全部文件編程結束。 數(shù)據查詢：AT89S51單片機用數(shù)據查詢方式來檢測一個寫周期是否結束，在一個寫周期中，如需讀取最后寫入的哪個字節(jié)，則讀出的數(shù)據最高位（P0.7）是原來寫入字節(jié)最高位的反碼。寫周期完成后，有效的數(shù)據就會出現(xiàn)在所有輸出端上，此時，可進入下一個字節(jié)的寫周期，寫周期開始后，可在任意時刻進行數(shù)據查詢。 Ready/:字節(jié)編程的進度要通過“RDY/BSY”輸出信號監(jiān)測，編程期間，ALE變?yōu)楦唠娖健癏”后P3.0端電平被拉低，表示正在編程狀態(tài)（忙狀態(tài)）。編程完成后，可在任意時刻進行數(shù)據查詢。 程序校驗：如果加密位LB1、LB2沒有進行編程，則代碼數(shù)據可通過地址和數(shù)據線讀回原編寫的數(shù)據，各加密位也可通過直接回讀進行校驗。 讀片內簽名字節(jié)：AT89S51單片機內由3個簽名字節(jié)，地址為000H、100H和200H。用于聲明該器件的廠商和型號等信息，讀簽名字節(jié)的過程和正常校驗相仿，只需將P3.6和P3.7保持低電平，返回值意義如下： （000H）=1EH 聲明產品由ATMEL公司制造。 （100H）=51H聲明為AT89S51單片機 （200H）=06H 芯片的擦除：在并行編程模式，利用控制信號的正確組合并保持ALE/引腳200ns——500ns的低電平脈沖寬度即可完成擦除操作。 在串行編程模式，芯片擦除操作是利用擦除指令進行的。在這種方式，擦除周期時自身定時的，大約位500MS。 擦除期間，用串行方式讀任何地址數(shù)據，返回值均為00H。 Flash閃速存儲器的串行編程：將RST接到Vcc，程序代碼存儲器陣列可通過串行ISP接口進行編程，串行接口包含SCK線、MOSI（輸出）線。將RST拉高后，在其他操作前必須發(fā)出編程使能指令，編程前需要將芯片擦除。 芯片擦除則將存儲代碼陣列全寫位FFH。 外部系統(tǒng)時鐘信號需接到XTAL端或者在XTAL1和XTAL2接上晶體振蕩器。最高的串行時鐘（SCK）不超過1/16晶體時鐘，當晶體為33MHZ時，最大SCK頻率為2MHZ。 Flash閃速存儲器的串行編程方法：對AT89S51的串行編程次序推薦使用以下方法： 1. 上電次序：將電源家在Vcc和GND引腳，RST置為”H”，如果XTAL1和XTAL2接上晶體或者在XTAL1接上3-33MHZ的時鐘頻率，等候10MS。 2. 將編程使能指令發(fā)送到MOSI(Pin1.5)，編程時鐘接至SCK（pin1.7），次頻率需小于晶體時鐘頻率的1/16. 3. 代碼陣列的編程可選字節(jié)模式或者頁模式。寫周期時自身定時的，一般不大于0.5ms（5v電壓時）。 4. 任意代碼單元均可MISO（pin1.6）和讀指令選擇相應的地址回讀數(shù)據進行校驗。 5. 編程結束應將RST置為“L”以結束操作。 6. 斷電次序：如果需要的話，按這個方法斷電，加入沒有使用晶體，將XTAL置為低，RST置為低，關斷Vcc。 數(shù)據校驗：數(shù)據校驗也可在串行模式下進行，在這個模式，在一個寫周期中，通過輸出引腳MISO串行回讀一個字節(jié)數(shù)據的最高位將為最后寫入字節(jié)的反碼。 串行指令編程設置：串行編程指令設置為一個4字節(jié)的協(xié)議，參見表8. 并行編程接口：采用控制信號的正確組合可對Flash閃速存儲陣列中的每一代碼字節(jié)進行寫入和存儲器的整片擦除，寫操作周期是自身定時的，初始化后它將會自動定時到操作完成。 更多的有關ATMEL系列單片機的編程計數(shù)請聯(lián)系相應的編程器供應商以獲取最新的軟件版本。 表7 Flash編程模式： 注：1.芯片擦除每一脈沖為200ns—500ns。 2.寫代碼數(shù)據每一脈沖為200ns—500ns。 3.寫加密位每一脈沖為200ns—500ns。 4.編程期間P3.0引腳輸出RDY/信號。 5.“X”不需要理會。 圖4 Flash存儲器編程（并口模式） 圖5 Flash存儲器校驗（并口模式） Flash編程和校驗特性（并行模式）： 圖6 Flash編程和校驗波形（并行模式） Flash存儲器的串行下載： Flash編程和校驗波形（串行模式）： 表8 串行編程指令： 注：1.當LB3和LB4加密位已編程時則不可讀簽名字節(jié)。 2.B1=0 B2=0,方式1，無加密保護 B1=0 B2=1,方式2，加密位LB1 各個加密位在方式4執(zhí)行前需按順序逐一操作 B1=1 B2=0,方式3，加密位LB2 B1=1 B2=1,方式4，加密位LB3 復位信號為”H”后，建立數(shù)據前使SCK為低電平至少64個系統(tǒng)時鐘周期，復位脈沖時必須的。SCK時鐘頻率不得大于XTAL1時鐘的1/16. 在頁讀/寫模式，數(shù)據總是從地址00開始直到255.命令字節(jié)后緊跟著高4位地址，全部數(shù)據單元256字節(jié)會逐一進行讀/寫，此時下個指令將準備譯碼。 串行編程特性： 圖9 串行編程時序 極限參數(shù)： 注：這些參數(shù)是器件的極限參數(shù)，使用條件必須在上述列表范圍以內，如果超出上述條件，器件就不能得到安全保證甚至可能造成永久性破壞。 DC參數(shù)： 注：以下參數(shù)測試條件：在TA=40°C—85°C，Vcc=4.0v—5.5v 注： 1.在穩(wěn)定狀態(tài)（無輸出）條件下，Iol有以下限制：每一引腳最大Iol為10mA，每一8位端口p0為26mA，P1、P2、P3為15mA。 全部輸出引腳最大Iol為71mA。 2.掉電模式的最小Vcc為2v。 AC特性： 在以下工作條件測得：P0、ALE/PROG和PSEN負載容抗為100pF，其他端口負載容抗為80PF。 外部程序和數(shù)據存儲器特性： 外部程序存儲器讀周期： 外部數(shù)據存儲器讀周期： 外部程序存儲器寫周期： 外部數(shù)據存儲器寫周期： 外部時鐘驅動時序： 串行口時序： 在Vcc=4.0v—5.5v，負載電容為80pF條件下： 上位寄存器時序波形： AC測試輸入/輸出波形; 注：AC輸入測試在Vcc-0.5v邏輯1及0.45v為邏輯0，時序測試在VIH為最小是和VIL為最大測量。 浮空波形： 注：在浮空狀態(tài)，端口引腳在負載出現(xiàn)100mv電壓變化時即為浮空，也即當一個端口電壓從VOH到VOL變化時出現(xiàn)100mv電壓時浮空狀態(tài)。 產品信息： 封裝形式： [1] S. P. Amarasinghe, J. M. Anderson, M. S. Lam, and C.-W.Tseng, “An overview of the SUIF compiler for scalable parallel machines,” Proceedings of the Seventh SIAM Conference onParallel Processing for Scientific Compiler, San Francisco, 1995. [2] S. Amarasinghe et.al., “Hot compilers for future hot chips,” presented at Hot Chips VII, Stanford, CA, 1995. [3] D. W. Anderson, F. J. Sparacio, and R. M. Tomasulo, “The IBM System/360 model 91: Machine philosophy and instruction-handling,” IBM Journal of Research and Development, vol. 11, pp. 8–24, 1967. 22 本科生畢業(yè)論文（設計） 英文原文 原文出處： DOUGLASLP.VHDL：programming by example[M]．New York：McGraw—Hill Professional2002． FOREWORD VHDL has been at the heart of electronic design productivity since initial ratification by the IEEE in 1987. For almost 15 years the electronic design automation industry has expanded the use of VHDL from initial concept of design documentation, to design implementation and func tional verification. It can be said that VHDL fueled modern synthesis technology and enabled the development of ASIC semiconductor compa nies. This book has served as the authoritative source of practical information on the use of VHDL for users of the language around the world. The use of VHDL has evolved and its importance increased as semi conductor devices dimensions have shrunk. Not more than 10 years ago it was common to mix designs described with schematics and VHDL. But as design complexity grew, the industry abandoned schematics in favor of the hardware description language only. The successive revisions of this book have always kept pace with the industry’s evolving use of VHDL. The fact that VHDL is adaptable is a tribute to its architecture. The industry has seen the use of VHDL’s package structure to allow design ers, electronic design automation companies and the semiconductor indus try to experiment with new language concepts to ensure good design tool and data interoperability. When the associated data types found in the IEEE 1164 standard were ratified, it meant that design data interoper ability was possible. All of this was facilitated by industry backing in a consortium of systems, electronic design automation and semiconductor companies now known as Accellera. And when the ASIC industry needed a standard way to convey gate-level design data and timing information in VHDL, one of Accellera’s progenitors (VHDL International) sponsored the IEEE VHDL team to build a companion standard. The IEEE 1076.4 VITAL (VHDL Initiative Towards ASIC Libraries) was created and ratified as offers designers a single language flow from concept to gate-level signoff. In the late ’90s, the Verilog HDL and VHDL industry standards teams collaborated on the use of a common timing data such as IEEE 1497 SDF, set register transfer level (RTL) standards and more to improve design methodologies and the external connections provided to the hardware description languages. But from the beginning, the leadership of the VHDL community has assured open and internationally accredited standards for the electronic design engineering community. The legacy of this team’s work continues to benefit the design community today as the benchmark by which one measures openness. The design community continues to see benefits as the electronic design automation community continues to find new algorithms to work from VHDL design descriptions and related standards to again push designer productivity.And, as a new generation of designers of programmable logic devices move to the use of hardware description languages as the basis of their design methodology, there will be substantial growth in the number of VHDL users. This new generation of electronic designers, along with the current designers of complex systems and ASICs, will find this book invaluable . Updated with current ue of the standard, all will benefit from the years of use that have made the VHDL language the underpinning of successful electronic design. Introduction to VHDL The VHSIC Hardware Description Language is an industry standard language used to describe hardware from the abstract to the concrete level. VHDL resulted from work done in the ’70s and early ’80s by the U.S. Department of Defense. Its roots are in the ADA language, as will be seen by the overall structure of VHDL as well as other VHDL statements. VHDL usage has risen rapidly since its inception and is used by literally tens of thousands of engineers around the globe to create sophisticated electronic products. This chapter will start the process of easing the reader into the complexities of VHDL. VHDL is a powerful language with numerous language constructs that are capable of describing very complex behavior. Learning all the features of VHDL is not a simple task. Complex features will be introduced in a simple form and then more complex usage will be described. In 1986, VHDL was proposed as an IEEE standard. It went through a number of revisions and changes until it was adopted as the IEEE 1076 standard in December 1987. The IEEE 1076-1987 standard VHDL is the VHDL used in this book.(Appendix D contains a brief description of VHDL 1076-1993.) All the examples have been described in IEEE 1076 VHDL, and compiled and simulated with the VHDL simulation environment from Model Technology Inc. VHDL Terms Before we go any further, let’s define some of the terms that we use throughout the book. These are the basic VHDL building blocks that are used in almost every description, along with some terms that are redefined in VHDL to mean something different to the average designer. Entity. All designs are expressed in terms of entities. An entity is the most basic building block in a design. The uppermost level of the design is the top-level entity. If the design is hierarchical, then the top-level description will have lowerlevel descriptions contained in it. These lower-level descriptions will be lowerlevel mentities contained in the top-level entity description. Architecture. All entities that can be simulated have an architecture description. The architecture describes the behavior of the entity. A single entity can have multiple architectures. One architecture might be behavioral while another might be a structural description of the design. Configuration. A configuration statement is used to bind a component instance to an entity-architecture pair. A configuration can be considered like a parts list for a design. It describes which behavior to use for each entity, much like a parts list describes which part to use for each part in the design. Package. A package is a collection of commonly used data types and subprograms used in a design. Think of a package as a toolbox that contains tools used to build designs. Driver. This is a source on a signal. If a signal is driven by two sources, then when both sources are active, the signal will have two drivers. Bus. The term “bus” usually brings to mind a group of signals or a particular method of communication used in the design of hardware. In VHDL, a bus is a special kind of signal that may have its drivers turned off. Attribute. An attribute is data that are attached to VHDL objects or predefined data about VHDL objects. Examples are the current drive capability of a buffer or the maximum operating temperature of the device. Generic. A generic is VHDL’s term for a parameter that passes information to an entity. For instance, if an entity is a gate level model with a rise and a fall delay, values for the rise and fall delays could be passed into the entity with generics. Process. A process is the basic unit of execution in VHDL. All operations that are performed in a simulation of a VHDL description are broken into single or multiple processes. Describing Hardware in VHDL VHDL Descriptions consist of primary design units and secondary design units. The primary design units are the Entity and the Package. The secondary design units are the Architecture and the Package Body. Secondary design units are always related to a primary design unit. Libraries are collections of primary and secondary design units. A typical design usually contains one or more libraries of design units. Entity A VHDL entity specifies the name of the entity, the ports of the entity, and entityrelated information. All designs are created using one or more entities. Let’s take a look at a simple entity example: ENTITY mux IS PORT ( a, b, c, d : IN BIT;s0, s1 : IN BIT; x, : OUT BIT); END mux; The keyword ENTITY signifies that this is the start of an entity statement. In the descriptions shown throughout the book, keywords of the language and types provided with the STANDARD package are shown in ALL CAPITAL letters. For instance, in the preceding example, the keywords are ENTITY, IS, PORT, IN, INOUT, and so on. The standard type provided is BIT. Names of user-created objects such as mux, in the example above, will be shown in lower case. The name of the entity is mux. The entity has seven ports in the PORT clause. Six ports are of mode INand one port is of mode OUT. The four data input ports (a, b, c, d) are of type BIT. The two multiplexer select inputs, s0 and s1, are also of type BIT. The output port is of type BIT. The entity describes the interface to the outside world. It specifies the number of ports, the direction of the ports, and the type of the ports. A lot more information can be put into the entity than is shown here, but this gives us a foundation upon which we can build more complex examples. Architectures The entity describes the interface to the VHDL model. The architecture describes the underlying functionality of the entity and contains the statements that model the behavior of the entity. An architecture is always related to an entity and describes the behavior of that entity. An architecture for the counter device described earlier would look like this: ARCHITECTURE dataflow OF mux ISSIGNAL select : INTEGER; BEGIN select <= 0 WHEN s0 = ‘0’ AND s1 = ‘0’ ELSE1 WHEN s0 = ‘1’ AND s1= ‘0’ ELSE2 WHEN s0 = ‘0’ AND s1 = ‘1’ ELSE3; x <= a AFTER 0.5 NS WHEN select = 0 ELSEb AFTER 0.5 NS WHEN select = 1 ELSEc AFTER 0.5 NS WHEN select = 2 ELSEd AFTER 0.5 NS; END dataflow; The keyword ARCHITECTURE signifies that this statement describes an architecture for an entity. The architecture name is dataflow. The entity the architecture is describing is called mux. The reason for the connection between the architecture and the entity is that an entity can have multiple architectures describing the behavior of the entity. For instance, one architecture could be a behavioral description, and another could be a structural description. The textual area between the keyword ARCHITECTURE and the keyword BEGIN is where local signals and components are declared for later use.In this example signal select is declared to be a local signal. The statement area of the architecture starts with the keyword BEGIN. All statements between the BEGINand the ENDnetlist statement are called concurrent statements, because all the statements execute concurrently. Default Configurations The simplest form of explicit configuration is the default configuration. This configuration can be used for models that do not contain any blocks or components to configure. The default configuration specifies the configuration name, the entity being configured, and the architecture to be used for the entity. Following is an example of two default configurations shown by configurations big_count and small_count: LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY counter IS PORT(load, clear, clk : IN std_logic; PORT(data_in : IN INTEGER; PORT(data_out : OUT INTEGER); END counter; ARCHITECTURE count_255 OF counter IS BEGIN PROCESS(clk) VARIABLE count : INTEGER := 0; BEGIN IF clear = ‘1’ THEN count := 0; ELSIF load = ‘1’ THEN count := data_in; ELSE IF (clk’EVENT) AND (clk = ‘1’) AND (clk’LAST_VALUE = ‘0’) THEN IF (count = 255) THEN count := 0; ELSE count := count + 1; END IF; END IF; END IF; data_out <= count; END PROCESS; END count_255; ARCHITECTURE count_64k OF counter IS BEGIN PROCESS(clk) VARIABLE count : INTEGER := 0; BEGIN IF clear = ‘1’ THEN count := 0; ELSIF load = ‘1’ THEN count := data_in; ELSE IF (clk’EVENT) AND (clk = ‘1’) AND (clk’LAST_VALUE = ‘0’) THEN IF (count = 65535) THEN count := 0; ELSE count := count + 1; END IF; END IF; END IF; data_out <= count; END PROCESS; END count_64k; CONFIGURATION small_count OF counter IS FOR count_255 END FOR; END small_count; CONFIGURATION big_count OF counter IS FOR count_64k END FOR; END big_count; This example shows how two different architectures for a counter entity can be configured using two default configurations. The entity for the counter does not specify any bit width for the data to be loaded into the counter or data from the counter. The data type for the input and output data is INTEGER.With a data type of integer, multiple types of counters can be supported up to the integer representation limit of the host computer for the VHDL simulator. The two architectures of entity counter specify two different-sized counters that can be used for the entity. The first architecture, count_255, specifies an 8-bit counter. The second architecture, count_64k, specifies a 16-bit counter. The architectures specify a synchronous counter with a synchronous load and clear. All operations for the device occur with respect to the clock. Each of the two configurations for the entity specifies a different architecture for the counter entity. Let’s examine the first configuration in more detail. The configuration design unit begins with the keyword CONFIGURATION and is followed by the name of the configuration. In this example, the name of the configuration is small_count. The keyword OF precedes the name of the entity BEGIN configured (counter). The next line of the configuration starts the block configuration section. The keyword FOR is followed by a name of the architecture to use for the entity being configured or the name of the block of the architecture that will be configured. Any component or block configuration information then exists between the FOR ARCHITECTURE clause and the matching END FOR. In this architecture, there are no blocks or components to configure; therefore, the block configuration area from the FOR clause to the END FOR clause is empty, and the default is used. The configuration is called the default configuration, because the default is used for all objects in the configuration. The first configuration is called small_count and binds architecture count_255 with entity counter to form a simulatable object. The second configuration binds architecture count_64k with entity counter and forms a simulatable object called big_count. 第 9 頁 共 9 頁