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1、200V功率SOI-LIGBT器件熱載流子退化機(jī)理及壽命模型研究 碩士研究生畢業(yè)論文 學(xué)號(hào)：080978 劉斯揚(yáng) 指導(dǎo)教師：時(shí)龍興 專業(yè)：微電子學(xué)與固體電子學(xué) 答辯時(shí)間：2011年2月19日 摘 要 功率集成電路提高了整機(jī)系統(tǒng)的穩(wěn)定性和可靠性，已在國民經(jīng)濟(jì)各領(lǐng)域中發(fā)揮了重要的作用。SOI(Silicon-On-Insulator, SOI)介質(zhì)全隔離的實(shí)現(xiàn)有助于減小各種寄生效應(yīng)，而橫向絕緣柵雙極型晶體管（LIGBT）器件具有擊穿電壓高、導(dǎo)通電阻低且易與標(biāo)準(zhǔn)CMOS工藝兼容的特點(diǎn)，因此， SOI-LIGBT器件非常適用于功率集成電路。然而，SOI-LIG

2、BT器件通常工作在高溫、高壓及大功率環(huán)境中，熱載流子效應(yīng)嚴(yán)重，同時(shí)，器件中特有的空穴電流分量又會(huì)加劇熱載流子退化。因此SOI-LIGBT器件的熱載流子可靠性問題將阻礙SOI-LIGBT器件及相關(guān)功率集成電路的進(jìn)一步發(fā)展，迫切需要對(duì)其展開深入研究。 本文通過借助Tsuprem4與Medici等仿真工具以及I-V特性法與電荷泵（CP）法等實(shí)測(cè)方法深入研究了PDP掃描驅(qū)動(dòng)芯片用200V SOI-LIGBT器件的熱載流子退化機(jī)理。研究結(jié)果表明：在低Vgs高Vds條件下的主要退化機(jī)理是熱空穴注入積累區(qū)與靠近積累區(qū)的場(chǎng)氧化層，表現(xiàn)為器件導(dǎo)通電阻Ron在應(yīng)力初期有所下降，隨后又隨著應(yīng)力時(shí)間的增加而增加；而

3、在高Vgs低Vds條件下的主要退化機(jī)理是熱電子注入柵氧化層，表現(xiàn)為開啟電壓Vth的正向漂移。另外，本文還首次提出SOI-LIGBT器件的空穴電流分量對(duì)熱載流子退化有重要影響。研究結(jié)果表明：由于空穴電流分量的存在導(dǎo)致SOI-LIGBT器件的熱載流子退化程度明顯強(qiáng)于具有相同工藝和結(jié)構(gòu)參數(shù)的SOI-LDMOS器件。 最后，本文基于SOI-LIGBT器件熱載流子退化機(jī)理的研究結(jié)果建立了導(dǎo)通電阻Ron的熱載流子退化壽命模型，并基于測(cè)試結(jié)果提取了模型中的相關(guān)參數(shù)。實(shí)驗(yàn)證明所建立的退化壽命模型可以較為準(zhǔn)確地預(yù)測(cè)導(dǎo)通電阻的退化，從而為研制長壽命的SOI-LIGBT器件提供了可靠的理論指導(dǎo)。 關(guān)鍵詞：功率S

4、OI-LIGBT，功率集成電路，熱載流子效應(yīng)，壽命模型 Abstract The birth of the Power Integrated Circuit (PIC) improved the whole electronic system's stability and reliability, and hence played an important role in all fields of our life.The implementation of the SOI (Silicon-On-Insulator) full dielectric isolation is he

5、lpful to reduce all kinds of parasitic effects, Lateral Insulated Gate Bipolar Transistor (LIGBT) behaves with high breakdown voltage, low on-resistance and is compatible with standard CMOS process easily, consequently, SOI-LIGBT is fit for the application in PIC. Nevertheless, the SOI-LIGBT device

6、always operates at high temparature, high voltage and high power, as a result, it suffers from hot-carrier effects seriously. At the same time, the special hole current component in SOI-LIGBT device can make the hot-carrier effects much more serious. The hot-carrier reliability in SOI-LIGBT device w

7、ill be an obstacle to the development of SOI-LIGBT and related PIC, and an in-depth research on hot carrier is being called upon to. In this thesis, the hot-carrier degradation mechanism of 200V SOI-LIGBT using in PDP scan driver IC was investigated by Tsuprem4, Medici simulations and I-V character

8、istic measurements, charge pumping (CP) method. It showed that the main degradation mechanism under low Vgs and high Vds stress condition was hot hole injection into the accumulation area and the field oxide closing the accumulation area, resulting in on-resistance (Ron) decrease at the early stress

9、 stage and increase after undergoing some time of stress, however, under high Vgs and low Vds stress condition, the main degradation mechanism was hot electron injection into the gate oxide, causing the positive shift of the threshold voltage (Vth). Moreover, the important influence upon hot-carrier

10、 degradation from the hole current compent in SOI-LIGBT device was proposed firstly, it showed that the hot carrier degradation level was much more serious than that in SOI-LDMOS with the fully same structure and process parameters. Finally, a hot-carrier degradation lifetime model about Ron was gi

11、ven basing the hot-carrier degradation mechanisms of SOI-LIGBT device, and the related parameters in the model were extracted basing the measurement results. The experiments indicated that the lifetime model could be used to forecast the degradation of Ron accurately, which results provided theoreti

12、cal instruction for developing long life-time SOI-LIGBT device. Keywords: power SOI-LIGBT, PIC, hot-carrier effect, lifetime model 600V Trench超結(jié)VDMOS器件的設(shè)計(jì) 碩士研究生畢業(yè)論文 學(xué)號(hào)：080982 祝靖 指導(dǎo)教師：孫偉鋒 專業(yè)：微電子學(xué)與固體電子學(xué) 答辯時(shí)間：2011年2月19日 摘 要 功率MOSFET器件是功率集成電路系統(tǒng)中的核心部分之一,其性能優(yōu)劣直接影響功率集成系統(tǒng)產(chǎn)品的競爭力。傳統(tǒng)功率V

13、DMOS器件的導(dǎo)通電阻和擊穿電壓存在2.5次方的關(guān)系，這種關(guān)系被人們稱為“硅限”，這種“極限”是器件功耗進(jìn)一步降低的瓶頸。為此，理論界提出了超結(jié)原理，并研究出新型超結(jié)功率VDMOS器件。此后的數(shù)十年里，超結(jié)VDMOS器件在結(jié)構(gòu)設(shè)計(jì)和工藝制造上得到了快速發(fā)展。 本文采用理論分析、TCAD軟件輔助以及工藝流片相互結(jié)合的方法，設(shè)計(jì)了一款基于深槽刻蝕工藝的600V超結(jié)VDMOS器件。本文首先簡要的介紹了VDMOS器件及其發(fā)展，詳細(xì)分析了超結(jié)結(jié)構(gòu)及其耐壓原理；然后重點(diǎn)研究了Trench超結(jié)VDMOS器件的靜態(tài)參數(shù)和動(dòng)態(tài)參數(shù)及其影響因素，其中所研究的靜態(tài)參數(shù)主要包括了器件的擊穿電壓、導(dǎo)通電阻和閾值電壓等

14、，動(dòng)態(tài)參數(shù)主要包括了器件中各電容、體二極管反向恢復(fù)時(shí)間及雪崩耐量等。研究發(fā)現(xiàn)電荷不平衡效應(yīng)對(duì)器件原胞結(jié)構(gòu)不利，但在一定程度上有利于提高器件終端結(jié)構(gòu)的耐壓水平，因?yàn)殡姾刹黄胶?p>n)效應(yīng)有利于橫向耗盡，并且在終端結(jié)構(gòu)邊緣引入峰值電場(chǎng)，由此本文提出了一種新型終端結(jié)構(gòu)。最后，基于以上的理論分析，結(jié)合模擬仿真手段，通過參數(shù)優(yōu)化設(shè)計(jì)出了一款600V Trench超結(jié)VDMOS器件。 流片得到的Trench超結(jié)VDMOS器件分別用高壓半導(dǎo)體分析儀Agilent B1505和一套自主開發(fā)的模擬應(yīng)用測(cè)試系統(tǒng)，對(duì)各參數(shù)進(jìn)行了測(cè)試驗(yàn)證，結(jié)果表明該器件擊穿電壓可達(dá)695V，特征導(dǎo)通電阻為35mΩ·cm2，雪崩耐

15、量大于300mJ，體二極管恢復(fù)時(shí)間為300ns，達(dá)到了用于600V開關(guān)電源系統(tǒng)的設(shè)計(jì)目標(biāo)要求。 關(guān)鍵詞：功率器件；超結(jié)；靜態(tài)參數(shù)；動(dòng)態(tài)參數(shù)；深槽刻蝕 Abstract Power semiconductor device plays a crucial part in the PIC system, which impacts the performance of the whole system greatly. Breakdown voltage of the tranditional MOSFET-VDMOS has a relationship of 2.5 orders t

16、o the on-resistance, which is called “silicon limit”, exerting negative effects on minimizing the power dissipation.To solve this problem, the theory of superjunction was proposed, and since a novel power device SJVDMOs came out, the technology has begun to boom both in the structure and process des

17、ign. Based on the deep etch technology process, a trench SJVDMOS is designed in this work. Firstly the basic idea about how the SJ structure works is introduced, then we talk about the impact of different device parameters on the static characteristic containing breakdown voltage, on-resistance, th

18、reshold voltage, etc, and dynamic characteristic such as parasitic capacitance, reverse recovery time of the body diode and avalanche robustness. In addition, a novel terminal structure is proposed after research on the charge imbalance effect, concluding it is positive for improving BV of the termi

19、nal structure, although harmful for the cell region. The charge imbalance effect (p>n) in terminal structure contribute to transvers depletion and lead to an peak electric field in the edge. The structure is at last confirmed after optimizing the parameters making use of TCAD tools. High voltage se

20、miconduct analysor like Agilent B1505 and an original test system are employed to carry out tests on the device, to get detailed information of all the parameters concerned. The results show that the breakdown voltage of the device designed in this work is 695V with its on-resistance 35mΩ·cm2, besi

21、des the avalanche robustness reaches more than 300mJ while the body diode reverse recovery time is merely 300ns, from which we can confirm that it meet the requirement of a 600V Power management system perfectly. Keywords: Power device；Super junction；Static parameters；Dynamic parameters；Deep trench

22、 etching 8位40 MS/s低功耗ADC設(shè)計(jì) 碩士研究生畢業(yè)論文 學(xué)號(hào)：080911 顧俊輝 指導(dǎo)教師：吳建輝 專業(yè)：微電子學(xué)與固體電子學(xué) 答辯時(shí)間：2011年3月19日 摘 要 模數(shù)轉(zhuǎn)換器（ADC）和數(shù)模轉(zhuǎn)換器（DAC）是模擬世界與數(shù)字系統(tǒng)之間的橋梁。與流水線ADC相比，逐次逼近ADC以“開關(guān)”操作取代“放大”操作，取消了運(yùn)放從而允許更大的信號(hào)擺幅并具有更小的內(nèi)部噪聲；以數(shù)字電路為主的電路結(jié)構(gòu)則使其能夠充分地受益于更小的工藝特征尺寸。 論文討論了中等速度中等精度逐次逼近ADC的設(shè)計(jì)方法，首先從功耗最優(yōu)的角度確定了ADC的整體結(jié)構(gòu)以及

23、工作時(shí)序，提出了一種新的低開關(guān)能量DAC陣列結(jié)構(gòu)，設(shè)計(jì)了一種基于預(yù)充電邏輯的異步控制器，降低了控制器部分的功耗并避免了高頻率的驅(qū)動(dòng)時(shí)鐘信號(hào)；建立了ADC的系統(tǒng)級(jí)模型，分析了多種非理想因素對(duì)ADC整體性能的影響，在此基礎(chǔ)上完成了ADC的指標(biāo)分配，并基于SMIC 0.13μm 單層多晶八層金屬CMOS工藝完成了電路設(shè)計(jì)：優(yōu)化了ADC采樣開關(guān)及其驅(qū)動(dòng)電路以降低采樣失真，在綜合考慮了失調(diào)、噪聲、亞穩(wěn)態(tài)等因素的基礎(chǔ)上完成了比較器設(shè)計(jì)，以及ADC控制邏輯和自適應(yīng)環(huán)路延遲調(diào)整模塊的電路級(jí)設(shè)計(jì)。 本論文完成了ADC版圖設(shè)計(jì)及后仿真。結(jié)果表明，在40MS/s的采樣速率下，2.34375MHz，-1dBFs單音

24、正弦信號(hào)輸入時(shí)，ADC輸出SINAD為47.9dB，SFDR為50.2dB，功耗553.1μW，功耗優(yōu)質(zhì)因子FoM為68.2fJ / (conversion·step)，其性能指標(biāo)達(dá)到了設(shè)計(jì)要求。 關(guān)鍵詞：低功耗，逐次逼近ADC，異步控制器，開關(guān)能量，比較器，功耗優(yōu)質(zhì)因子 Abstract ADCs and DACs represent a link between digital systems and the real world. In recent years, SAR ADCs become more attractive when comparing with Pipel

25、ined ADCs. Switching is preferred over amplifying in order to get rid of OPA issues, and greatly benefits from the scaled technology at the same time. Larger analog input range and lower inherent noise are achieved by using SAR architecture. A design procedure for moderate-resolution moderate-sampl

26、ing-rate SAR ADCs is presented. A power-optimized ADC architecture which includes a low switching energy DAC array and a precharge-logic asynchronous controller is proposed. System-level model for the SAR ADC is built to analyze the impacts of various non-idealities on overall performances and provi

27、de guidance for specification decomposition and transistor-level design. Transistor-level design is done using SMIC 0.13μm 1P8M CMOS process. An improved sampling switch and the corresponding driving circuit are developed to achieve better sampling linearity. A low-power comparator in consideration

28、of offset, noise, meta-stability, etc. is showed. Transistor-level design of ADC control logic and adaptive delay controller is also presented in this paper. The layout design of the proposed ADC is done. The post-simulation indicates that 47.9dB SINAD and 50.2dB SFDR is achieved under the conditio

29、n of 40MSps sampling rate and 2.34375MHz, -1dB single-tone sine-wave input. The total power consumption is 553.1μW, and FoM achieves 68.2fJ / (conversion·step). In general, the proposed ADC reaches high dynamic specifications while its power consumption remains relatively low. Keywords: low power,

30、SAR ADCs, asynchronous controller, switching energy, comparator, FoM Zigbee收發(fā)芯片內(nèi)嵌低功耗低相位噪聲VCO設(shè)計(jì) 碩士研究生畢業(yè)論文 學(xué)號(hào)：080930 楊世鐸 指導(dǎo)教師：吳建輝 專業(yè)：微電子學(xué)與固體電子學(xué) 答辯時(shí)間：2011年3月19日 摘 要 無線傳感器網(wǎng)絡(luò)（Wireless Sensor Network，WSN）是一種由傳感器節(jié)點(diǎn)構(gòu)成的短距離無線通信網(wǎng)絡(luò)，Zigbee傳輸協(xié)議在無線傳感器網(wǎng)絡(luò)中應(yīng)用最為廣泛。Zigbee無線收發(fā)芯片中，壓控振蕩器（Voltage-Cont

31、rolled Oscillator，VCO）是關(guān)鍵的組成模塊之一。低功耗、低相位噪聲的VCO設(shè)計(jì)，對(duì)提高收發(fā)系統(tǒng)的性能起到關(guān)鍵作用。 論文的主要工作是設(shè)計(jì)應(yīng)用于Zigbee無線收發(fā)芯片的低功耗、低相位噪聲VCO，采用中芯國際（SMIC）0.18μm CMOS工藝進(jìn)行設(shè)計(jì)。論文總結(jié)了VCO的研究現(xiàn)狀和研究背景，分析了低功耗、低相位噪聲VCO的設(shè)計(jì)原理。論文中設(shè)計(jì)的VCO采用開關(guān)電阻陣列提供尾電流，實(shí)現(xiàn)了VCO的工作電流的可控性，通過選擇尾電流大小，使其在較低的工作電流下可以實(shí)現(xiàn)較好的性能；同時(shí)采用互補(bǔ)交叉耦合型電感電容壓控振蕩器（LC-VCO），通過電流復(fù)用技術(shù)有效地降低功耗。VCO采用多邊帶

32、調(diào)諧，3位開關(guān)電容陣列將頻率調(diào)諧范圍分成8個(gè)頻率邊帶，實(shí)現(xiàn)了的頻率覆蓋范圍，同時(shí)降低了調(diào)諧增益，優(yōu)化了相位噪聲性能。諧振網(wǎng)絡(luò)中采用的變?nèi)莨苓B接結(jié)構(gòu)可以優(yōu)化電容的非線性特性，提高諧振網(wǎng)絡(luò)的品質(zhì)因數(shù)，使得相位噪聲性能進(jìn)一步得到提高。論文中同時(shí)設(shè)計(jì)了正交二分頻電路和VCO輸出緩沖電路。 本論文設(shè)計(jì)的VCO在SMIC進(jìn)行了流片。對(duì)設(shè)計(jì)的VCO進(jìn)行測(cè)試，測(cè)試結(jié)果顯示，VCO的調(diào)諧范圍覆蓋了，功耗低于，全頻段內(nèi)相位噪聲低于-112.47dBc/Hz@1MHz，滿足了系統(tǒng)的設(shè)計(jì)需求。 關(guān)鍵詞：壓控振蕩器，開關(guān)電阻陣列，多邊帶調(diào)諧，互補(bǔ)交叉耦合，電流復(fù)用 Abstract Wireless Sen

33、sor Network (WSN) is a kind of low power, short distance wireless communication network. Zigbee protocol is the most widely used in WSN. Voltage-Controlled Oscillator (VCO) is an important part of Zigbee wireless transceiver. Design of low power, low phase noise VCO plays an important role to improv

34、e wireless system. The main work of this thesis is to design a low power, low phase noise VCO which is used in Zigbee wireless transceiver. It was designed and fabricated in SMIC Corporation, using SMIC 0.18μm CMOS technology. In the first part, the research status and research background of VCO is

35、 summarized. And then, the design specific of low power, low phase noise VCO is analyzed. Tail current of the designed VCO is provided by Switch-Resistor Arrays, witch makes the operation current controllable. By selecting the operation current, make sure that, VCO can achieve good performance in lo

36、w current. The main structure of this designed VCO is Complementary Cross-Coupled LC-VCO. It makes the power lower effectively by using Current-Reuse technology. Multi-band tuning is also used in this VCO. 3-bit Switch-Capacitors Array is used to divide the frequency tuning range into 8 sub-bands. T

37、he frequency tuning range is from 4.578GHz~5.338GHz. According to Multi-Band Tuning, the tuning amplification is lower, and the phase noise is decreased too. On the other hand, a new connection structure of varactors can improve the quality factor of oscillation network. This can make the phase nois

38、e parameter optimize further. A quadratic divide-by-two circuit and a VCO output buffer circuit are designed in this thesis. The VCO designed in this thesis is fabricated in SMIC Corporation. Testing of the designed VCO is performed. According to the testing result, the tuning range of this VCO is

39、from 4.578GHz to 5.338GHz; the power consumption is lower than 4.14mW; the phase noise is below -112.47dBc/Hz@1MHz offset in all frequency bands. The design meets the requirements of this project. Keywords: Voltage-Controlled Oscillator, Switch-Resistor Arrays, Multi-Band Tuning, Complementary Cro

40、ss-Couple, Current-Reuse Zigbee收發(fā)芯片內(nèi)嵌寬范圍高精度可變?cè)鲆娣糯笃髟O(shè)計(jì) 碩士研究生畢業(yè)論文 學(xué)號(hào)：080943 胡超 指導(dǎo)教師：吳建輝 專業(yè)：微電子學(xué)與固體電子學(xué) 答辯時(shí)間：211年3月19日 摘 要 現(xiàn)代通信系統(tǒng)中，射頻輸入信號(hào)的動(dòng)態(tài)范圍很大，因此接收機(jī)通常需要一個(gè)自動(dòng)增益控制電路來提供恒定功率的信號(hào)給ADC，從而降低ADC的動(dòng)態(tài)范圍的要求。作為自動(dòng)增益控制環(huán)路的關(guān)鍵模塊之一，數(shù)字可變?cè)鲆娣糯笃鳎≒GA）的設(shè)計(jì)對(duì)整個(gè)接收機(jī)性能具有很大的影響。 本論文設(shè)計(jì)了一個(gè)用于Zigbee低中頻結(jié)構(gòu)收發(fā)機(jī)中的數(shù)字可變?cè)鲆娣糯?/p>

41、器（PGA）。首先介紹了自動(dòng)增益控制環(huán)路系統(tǒng)及PGA的設(shè)計(jì)理論，總結(jié)了各種PGA電路，之后根據(jù)Zigbee接收機(jī)的性能要求，確定了PGA的參數(shù)，給出了具體的設(shè)計(jì)方案。設(shè)計(jì)的PGA主要由三個(gè)固定增益級(jí)，一個(gè)單位增益緩沖級(jí)以及一個(gè)可變?cè)鲆婕?jí)組成的。為了保證單個(gè)固定增益級(jí)的增益精度以及線性度，采用了源退化電阻以及跨導(dǎo)提高結(jié)構(gòu)，并通過電容電阻補(bǔ)償進(jìn)行了頻率補(bǔ)償。可變?cè)鲆娣糯蠹?jí)采用閉環(huán)結(jié)構(gòu)，由反饋電阻網(wǎng)絡(luò)以及全差分運(yùn)算跨導(dǎo)放大器組成，為了減小功耗，全差分運(yùn)算跨導(dǎo)放大器采用了class-AB輸出級(jí)。 本論文基于SMIC 0.18μm CMOS工藝進(jìn)行了PGA的原理圖設(shè)計(jì)、版圖設(shè)計(jì)、后仿真以及測(cè)試。后仿

42、真結(jié)果表明，PGA能夠提供從-1.2dB到58.8dB的寬增益控制范圍，增益步長為1dB，通帶內(nèi)增益誤差為0.13dB，噪聲系數(shù)為29.1dB。測(cè)試結(jié)果表明，整個(gè)接收機(jī)成功實(shí)現(xiàn)了接收功能，PGA在8.5dB增益下的3dB帶寬大于8MHz，輸入三階交調(diào)點(diǎn)為14.5dBm。在1.8V電源電壓下，PGA總功耗為9.1mW。后仿真及測(cè)試結(jié)果滿足Zigbee接收機(jī)系統(tǒng)要求。 關(guān)鍵詞：自動(dòng)增益控制；數(shù)字可變?cè)鲆娣糯笃?；Zigbee收發(fā)機(jī)；頻率補(bǔ)償 Abstract In modern communication systems, the RF input signal has a wide dy

43、namic range, so the receiver usually need an Automatic Gain Control (AGC) circuit to provide a signal with constant power for ADC, which reduces the dynamic range requirement of ADC. As a key building block of AGC circuit, the Programmable Gain Amplifier (PGA) has a great influence on receiver perfo

44、rmance. A Programmable Gain Amplifier (PGA) was designed in this thesis for a Low-IF Zigbee transceiver. First, the AGC loop system and the design theory of PGA were presented, and various PGA circuits were summarized. Then, according to the Zigbee receiver performance requirements, the parameters

45、and topology of PGA were determined. This PGA was composed mainly of three fixed gain stages, one buffer and one programmable gain stage. In order to improve the gain accuracy and linearity of the fixed gain stage, the source degeneration resistor and gm boost structure were used, and the frequency

46、compensation was done by RC compensation. The programmable gain stage with close loop structure consisted of feedback resistor network and fully differential Operational Transconductance Amplifier (OTA). In order to save power, class-AB output structure was used in the fully differential OTA. The p

47、roposed PGA was designed, simulated and tested in SMIC 0.18μm CMOS technology. The post-simulation results indicated the PGA had a wide gain-variation range from -1.2dB to 58.8dB, and the gain step was 1dB with 0.13dB gain error at pass-band frequency, the noise figure was 29.1dB. The measurement re

48、sults indicated the receiver could achieve signal receiving function. At 8.5dB of gain, the 3dB bandwidth of PGA was greater than 8MHz, and the IIP3 was 14.5dBm. The whole PGA circuit consumed 9.1mW from a single 1.8V supply. The post-simulation and measure results met the Zigbee receiver performanc

49、e requirements. Keywords: Automatic Gain Control; Programmable Gain Amplifier; Zigbee transceiver;frequency compensation 嵌入式Linux功耗管理技術(shù)設(shè)計(jì)與實(shí)現(xiàn) 碩士研究生畢業(yè)論文 學(xué)號(hào)：080964 張黎明 指導(dǎo)教師：凌明 專業(yè)：微電子學(xué)與固體電子學(xué) 答辯時(shí)間：2011年3月19日 摘 要 隨著智能 、多媒體播放器等消費(fèi)電子的飛速發(fā)展，消費(fèi)者對(duì)便攜式電子產(chǎn)品的可持續(xù)工作時(shí)間的要求也不斷增長。而現(xiàn)代電池技術(shù)的發(fā)展進(jìn)步卻遠(yuǎn)遠(yuǎn)

50、落后于嵌入式系統(tǒng)對(duì)電池容量的要求，系統(tǒng)功耗成為嵌入式手持產(chǎn)品的設(shè)計(jì)瓶頸，嵌入式功耗管理技術(shù)成為解決這一問題的有效手段。 本文基于自主設(shè)計(jì)的嵌入式低功耗硬件平臺(tái)，通過系統(tǒng)休眠和系統(tǒng)運(yùn)行兩方面重點(diǎn)探討了在嵌入式Linux平臺(tái)下的功耗管理技術(shù)。本文首先介紹和分析了Linux休眠機(jī)制——高級(jí)電源管理APM?；贏PM技術(shù)，設(shè)計(jì)和實(shí)現(xiàn)了系統(tǒng)休眠的驅(qū)動(dòng)層、內(nèi)核適配層，并在此基礎(chǔ)上提出了基于閾值預(yù)測(cè)的系統(tǒng)休眠策略。其次，針對(duì)系統(tǒng)運(yùn)行時(shí)的功耗問題，基于動(dòng)態(tài)變頻的原理和Linux cpufreq子系統(tǒng)，給出了動(dòng)態(tài)變頻技術(shù)在驅(qū)動(dòng)層和內(nèi)核層的實(shí)現(xiàn)方案，并在傳統(tǒng)策略的基礎(chǔ)上重點(diǎn)設(shè)計(jì)了兩種改進(jìn)策略，使動(dòng)態(tài)變頻技術(shù)能夠

51、適應(yīng)不同應(yīng)用環(huán)境下的需求。此外，本文還給出了動(dòng)態(tài)時(shí)鐘供給、智能LCD背光調(diào)整、單個(gè)設(shè)備休眠/喚醒等其他幾種系統(tǒng)運(yùn)行時(shí)的技術(shù)。 最后，在課題硬件平臺(tái)上測(cè)試了本文所設(shè)計(jì)的功耗管理技術(shù)，實(shí)驗(yàn)結(jié)果表明：運(yùn)用本文所設(shè)計(jì)功耗管理技術(shù)的系統(tǒng)，休眠時(shí)功耗為系統(tǒng)全速運(yùn)行時(shí)的6%，接近硬件平臺(tái)的理論休眠功耗極限?；運(yùn)行時(shí)功耗比原有系統(tǒng)降低35%以上。且無論是在休眠時(shí)還是運(yùn)行時(shí)，課題系統(tǒng)功耗均低于主流手持設(shè)備平均水平，滿足嵌入式手持應(yīng)用的需求。 關(guān)鍵詞：嵌入式Linux；高級(jí)電源管理；系統(tǒng)休眠；動(dòng)態(tài)變頻；功耗策略；SEP4020 Abstract With the development of cons

52、umer electronics such as smart phone and Multimedia Player?, the consumers continuously increase the demands of the sustainable work time of portable electronic products. But, the progress of the modern battery technology is far behind the requirements of embedded system. So, the conflict between th

53、e power produced by the high performance product and the time the product can sustained is becoming more and more serious. The design and implimentation of power management technology become an effective way to reslove this problem. In this thesis, the power management technology based on the hardw

54、are platform and Linux system focuses on two parts?: one is the power consumption when the system is sleeping and the other one is the power consumption when the system is running. Firstly, the principle of system sleep which is APM technology in Linux is introduced. According to the APM technology,

55、 the driver layer and kernel layer is designed and implemented. Then ,based on the driver layer and kernel layer, the system sleep strategy is designed. Secondly, the dynamic frequency scaling technology during the system’s running time is analyzed. The thesis also gives the solution which involved

56、the design and implementation of the driver and kernel layer of dynamic frequency scaling technology. Then, two improved strategies are given on the basis of the traditional dynamic frequency scaling strategy, which can be adapt to the needs of different application environments. At last, more techn

57、ologies of running time such as dynamic clock supply and the scaling of the LCD’s backlight are given. The low power technologies are tested on the low-power hardware platform. The experimental results show that sleep?power consumption?accounts for?6% of?run-time?power consumption, which has been

58、to the limit of the hardware platform when the system is in sleeping mode. And the power consumption of system is 35% lower than the original system when the system is in running mode. The system energy consumption is also below the average power consumption of common handheld devices whether it is

59、in sleeping mode or running mode. Keywords?: embedded Linux?; advanced power management?; sleep mode?; dynamic frequency scaling?; power strategy?; SEP4020 無線傳感網(wǎng)絡(luò)接收芯片內(nèi)嵌混頻器設(shè)計(jì) 碩士研究生畢業(yè)論文 學(xué)號(hào)：080974 沈海峰 指導(dǎo)教師：時(shí)龍興 專業(yè)：微電子學(xué)與固體電子學(xué) 答辯時(shí)間：2011年3月19日 摘 要 基準(zhǔn)電壓源一般用來給其他電路模塊提供參考電壓，其性能高低直接影響整個(gè)系統(tǒng)

60、的性能。 論文設(shè)計(jì)了一種應(yīng)用于14bit 100MS/s高速高精度的數(shù)據(jù)轉(zhuǎn)換器的高性能基準(zhǔn)電壓源，包括帶隙基準(zhǔn)電壓源和基準(zhǔn)緩沖器電路。帶隙基準(zhǔn)電壓源是一種基于單電阻微調(diào)的曲率補(bǔ)償帶隙基準(zhǔn)電壓源：曲率補(bǔ)償電路是基于指數(shù)型曲率補(bǔ)償?shù)脑?，在傳統(tǒng)的一階溫度補(bǔ)償?shù)碾妷耗痘鶞?zhǔn)電壓源上完成的。基準(zhǔn)緩沖器是一種基于慢緩沖原理設(shè)計(jì)的緩沖器電路：緩沖器通過采用一種新穎的連接電路與片外電容相連，減弱了來自引線電感的不利影響；采用多級(jí)跨導(dǎo)增益級(jí)串聯(lián)而成的主運(yùn)放電路，為緩沖器提供了一個(gè)穩(wěn)定的高直流增益；采用正反饋回路結(jié)構(gòu)的電流增益級(jí)電路，提高了緩沖器驅(qū)動(dòng)負(fù)載的能力；另外通過設(shè)計(jì)一個(gè)獨(dú)立的極點(diǎn)來抵消片外電容與其等

61、效串聯(lián)電阻引入的零點(diǎn)，從而提高了緩沖器的穩(wěn)定性。 論文基于工藝，對(duì)所設(shè)計(jì)的基準(zhǔn)電壓源進(jìn)行了前仿真，版圖設(shè)計(jì)和后仿真。基準(zhǔn)電壓源的相關(guān)性能的后仿真結(jié)果為：帶隙基準(zhǔn)電壓源在的電源電壓下，-40℃到85℃范圍內(nèi)，經(jīng)過微調(diào)之后的曲率補(bǔ)償基準(zhǔn)電壓源的平均溫度系數(shù)達(dá)到了℃；當(dāng)電源電壓在變化時(shí)，其線性校準(zhǔn)率為；其電源電壓抑制比為-98dB@100Hz以及基準(zhǔn)緩沖器總輸出噪聲為，以上仿真結(jié)果均滿足設(shè)計(jì)指標(biāo)的需求。 關(guān)鍵詞：帶隙基準(zhǔn)電壓源、基準(zhǔn)緩沖器、微調(diào)電路、低溫漂、高電源抑制比、低噪聲 Abstract A reference voltage source is generally used t

62、o be a reference voltage for other circuit blocks and its performance directly affects the function of the whole circuit system. In this thesis, a high-performance reference voltage source, which is used in a 14bit 100MS/s high-speed, high-precision data converter, is designed. According to the pe

63、rformance requirements, the bandgap voltage reference and the reference buffer of the reference voltage source are designed in detail. The bandgap voltage reference is based on a single-trimming and curvature compensation. Its curvature compensation using the principle of exponential curvature compe

64、nsation is completed in the traditional first-order temperature compensation of the voltage-mode bandgap voltage reference. The reference buffer is based on the principle of a slow buffer. Using a novel circuit, its output is connected to the capacitor outside, which greatly reduces the bad effect f

65、rom the lead inductance. The main operational amplifier using multi-level transconductance amplifiers provides a stable and high DC gain. the current gain level using the positive feedback loop improves the ability to drive the load, and a separate pole is designed to offset a zero point that is gen

66、erated by the capacitor outside and its equivalent series resistance, which improves the stability of the buffer. The proposed circuit has been simulated with Chartered 0.18-μm process. The results of the post simulation are as follows. At the 1.8V supply voltage, and at the temperature from -40℃ to 85℃℃. The LNR is 31.7μV/V, when supply voltage changes from 1.4V to 2.6V. Its PSRR is -98dB@100Hz. The output noise peak-peak voltage of the reference buffer is 39.7μVrms. The simulation results abo