臥式車床數(shù)控化改造設(shè)計(jì)-縱向進(jìn)給系統(tǒng)設(shè)計(jì),臥式車床數(shù)控化改造設(shè)計(jì)-縱向進(jìn)給系統(tǒng)設(shè)計(jì),臥式,車床,數(shù)控,改造,設(shè)計(jì),縱向,進(jìn)給,系統(tǒng) SL811HS Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600 Document #: 38-08008 Rev. *A Revised March 14, 2002 SL811HS Embedded USB Host/Slave Controller SL811HS Document #: 38-08008 Rev. *A Page 2 of 29 TABLE OF CONTENTS 1.0 CONVENTIONS .4 2.0 DEFINITIONS .4 3.0 REFERENCES .4 4.0 INTRODUCTION .4 4.1 Block Diagram .4 4.2 SL811HS Host or Slave Mode Selection Master/Slave Mode .5 4.3 Features .5 4.4 Data Port, Microprocessor Interface .6 4.5 Interrupt Controller .6 4.6 Buffer Memory .6 4.7 PLL Clock Generator .6 4.8 USB Transceiver .8 5.0 SL811HS REGISTERS .8 5.1 Register Values on Power-up and Reset .9 5.2 USB Control Registers .9 5.3 SL811HS Control Registers .12 6.0 SL811HS AND SL811HST-AC PHYSICAL CONNECTIONS .16 6.1 SL811HS Physical Connections .16 6.2 SL811HST-AC Physical Connections .19 7.0 ELECTRICAL SPECIFICATIONS .22 7.1 Absolute Maximum Ratings .22 7.2 Recommended Operating Condition .22 7.3 External Clock Input Characteristics (X1) .22 7.4 DC Characteristics .23 7.5 USB Host Transceiver Characteristics .23 7.6 Bus Interface Timing Requirements .24 8.0 PACKAGE DIAGRAMS .28 LIST OF FIGURES Figure 4-1. SL811HS USB Host/Slave Controller Functional Block Diagram . 5 Figure 4-2. Full-Speed 48-MHz Crystal Circuit . 7 Figure 4-3. Optional 12-MHz Crystal Circuit . 7 Figure 6-1. SL811HS USB Host/Slave ControllerPin Layout . 16 Figure 6-2. SL811HST-AC USB Host/Slave Controller Pin Layout . 19 LIST OF TABLES Table 6-1. SL811HS Pin Assignments and Definitions .17 Table 6-2. SL811HST-AC Pin Assignments and Definitions .20 SL811HS Document #: 38-08008 Rev. *A Page 3 of 29 License Agreement Use of this document and the intellectual properties contained herein indicates acceptance of the following License Agreement. If you do not accept the terms of this License Agreement, do not use this document, or the associated intellectual properties, or any other material you received in association with this product, and return this document and the associated materials within fifteen (15) days to Cypress Semiconductor Corporation or (CY) or CYs authorized distributor from whom you purchased the product. 1. You can only legally obtain CYs intellectual properties contained in this document through CY or its authorized distributors. 2. You are granted a nontransferable license to use and to incorporate CYs intellectual properties contained in this document into your product. The product may be either for your own use or for sale. 3. You may not reverse-engineer the SL811HS or otherwise attempt to discover the designs of SL811HS. 4. You may not assign, distribute, sell, transfer or disclose CYs intellectual properties contained in this document to any other person or entity. 5. This license terminates if you fail to comply with any of the provisions of this Agreement. You agree upon termination to destroy this document, stop using the intellectual properties contained in this document and any of its modification and incorporated or merged portions in any form, and destroy any unused SL811HS chips. Warranty Disclaimer and Limited Liability Cypress (CY), hereafter referred to as the manufacturer, warrants that its products substantially conform to its specifications for a period of ninety (90) days from delivery as evidenced by the shipment records. The manufacturers sole obligation and liability for breaching the foregoing warranty shall be to replace or correct the defective products so that it substantially conforms to its specifications. Any modification of the products by anyone other than the manufacturer voids the foregoing warranty. No other warranties are expressed and none shall be implied. The manufacturer makes no warrant for the use of its products. In order to minimize risks associated with customers applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. The manufacturers products are not designed, authorized, or warranted suitable for use in life-support devices or systems or other critical applications. The manufacturer specifically excludes any implied warranties of merchantability and fitness for a particular purpose unless prohibited by law. In no event shall the manufacturers liability to you for damages hereunder for any cause whatsoever exceed the amount paid by you for the products. In no event will the manufacturer be liable for any loss of profits or other incidental or consequential damages arising out of the use or inability to use the product even if the manufacturer have been advised of the possibility of such damages. The manufacturer reserves the right to make changes at any time, without notice, to improve design or performance and supply the best product possible. The manufacturer assumes no responsibility for any errors that may appear in its technical document on the products nor does it make a commitment to update the information contained in its technical document. Nothing contained in the technical documents of the products shall be construed as a recommendation to use any products in violation of existing patents, copyrights or other rights of third parties. No license is granted by implication or otherwise under any patent, patent rights or other rights, of the manufacturer. SL811HS Document #: 38-08008 Rev. *A Page 4 of 29 1.0 Conventions 1,2,3,4 Numbers without annotations are decimals. Dh, 1Fh, 39h Hexadecimal numbers are followed by an “h.” 0101b, 010101b Binary numbers are followed by a “b.” bRequest, n Words in italics indicate terms defined by USB Specification or by this Specification. 2.0 Definitions USB Universal Serial Bus SL811HS The SL811HS is a Cypress USB Host/Slave Controller, providing multiple functions on a single chip. This part is offered in both a 28-pin PLCC package (SL811HS) and a 48-pin TQFP package (SL811HST-AC). Throughout this document, “SL811HS” refers to both packages unless otherwise noted. Note: This chip does not include CPU. SL11 The SL11 is a Cypress USB Peripheral Device Controller, providing multiple functions on a single chip. This part is offered in both a 28-pin PLCC package (SL11) and a 48-pin TQFP package (SL11T-AC). Throughout this document, “SL11” refers to both packages unless otherwise noted. Note: This chip does not include a CPU. SL11H The SL11H is a Cypress USB Host/Slave Controller, providing multiple functions on a single chip. This part is offered in both a 28-Pin PLCC package (SL11H) and a 48-Pin TQFP package (SL11HT-AC). Throughout this document, “SL11H” refers to both packages unless otherwise noted. Note: This chip does not include CPU. LSB Least Significant Bit MSB Most Significant Bit R/W Read/Write PLL Phase Lock Loop RAM Random Access Memory SIE Serial Interface Engine ACK Handshake packet indicates a positive acknowledgment. NAK Handshake packet indicating a negative acknowledgment USBD Universal Serial Bus Driver SOF Start of Frame is the first transaction in each frame. It allows endpoints to identify the start of the frame and synchronize internal endpoint clocks to the host. CRC Cyclic Redundancy Check HOST The host computer system on which the USB Host Controller is installed 3.0 References Ref 1 USB Specification 1.1: http:/www.usb.org. 4.0 Introduction 4.1 Block Diagram The SL811HS is an Embedded USB Host/Slave Controller capable of communicate with either full-speed or low-speed USB peripherals. The SL811HS can interface to devices such as microprocessors, microcontrollers, DSPs, or directly to a variety of buses such as ISA, PCMCIA, and others. The SL811HS USB Host Controller conforms to USB Specification 1.1. The SL811HS USB Host/Slave Controller incorporates USB Serial Interface functionality along with internal full-/low-speed trans- ceivers. The SL811HS supports and operates in USB full-speed mode at 12 Mbps, or at low-speed 1.5-Mbps mode. The SL811HS data port and microprocessor interface provide an 8-bit data path I/O or DMA bidirectional, with interrupt support to allow easy interface to standard microprocessors or microcontrollers such as Motorola or Intel CPUs and many others. Inter- nally, the SL811HS contains a 256-byte RAM data buffer which is used for control registers and data buffer. The available package types offered are a 28-pin PLCC (SL811HS) and a 48-pin TQFP package (SL811HST-AC). Both packages operate at 3.3 VDC. The I/O interface logic is 5V-tolerant. SL811HS Document #: 38-08008 Rev. *A Page 5 of 29 4.2 SL811HS Host or Slave Mode Selection Master/Slave Mode SL811HS can work in two modeshost or slave. For slave-mode operation and specification, please refer to the SL811S specification. This data sheet only covers host-mode operation. 4.3 Features The only USB Host/Slave controller for embedded systems in the market with a standard microprocessor bus interface. Supports both full-speed (12 Mbps) and low-speed (1.5 Mbps) USB transfer 4.3.1 USB Specification Compliance Conforms to USB Specification 1.1 4.3.2 CPU Interface Operates as a single USB host or slave under software control Low-speed 1.5 Mbps, and full speed 12 Mbps, in both master and slave modes Automatic detection of either low- or full-speed devices 8-bit bidirectional data, port I/O (DMA supported in slave mode) On-chip SIE and USB transceivers On-chip single root HUB support 256-byte internal SRAM buffer, ping-pong operation Operates from 12- or 48-MHz crystal or oscillator (built-in DPLL) 5 V-tolerant interface Suspend/resume, wake up, and low-power modes are supported Auto-generation of SOF and CRC5/16 Auto-address increment mode, saves memory Read/Write cycles Development kit including source code drivers is available Backward-compatible with SL11H, both pin and functionality 3.3V power source, 0.35 micron CMOS technology Available in both a 28-pin PLCC package (SL811HS) and a 48-pin TQFP package (SL811HST-AC). X1 X2 D+ D- INTR nWR nRD nCS nRST D0-7 GENERATOR USB Root-HUB XCVRS SERIAL INTERFACE ENGINE RAM BUFFERS CONTROL REGISTERS INTERRUPT CLOCK the maximum packet size for the ISO mode using the SL811HS is 255 16 bytes. When the Host Base Length register is set to zero, a Zero-Length packet will be transferred. 5.2.7 USB-A/USB-B Host PID, Device Endpoint (Write)/USB Status (Read) 03H, 0BH This register has two modes. When read, this register provides packet status and it contains information relative to the last packet that has been received or transmitted. The register is defined as follows. When written, this register provides the PID and Endpoint information to the USB SIE engine to be used in the next transaction. All sixteen Endpoints can be addressed by the SL811HS. PID3-0 4-bit PID Field (See Table Below) EP3-0 4-bit Endpoint Value in Binary. Bit Position Bit Name Function 0 ACK Transmission Acknowledge 1 Error Error detected in transmission 2 Time-out Time-out occurred 3 Sequence Sequence Bit. “0” if DATA0, “1” if DATA1 4 Setup “1” indicates Setup Packet 5 Overflow Overflow condition - maximum length exceeded during receives 6 NAK Slave returns NAK 7 STALL Slave set STALL bit D7 D6 D5 D4 D3 D2 D1 D0 PID3 PID2 PID1 PID0 EP3 EP2 EP1 EP0 PID TYPE D7-D4 SETUP 1101 (D Hex) IN 1001 (9 Hex) OUT 0001 (1 Hex) SOF 0101 (5 Hex) PREAMBLE 1100 (C Hex) NAK 1010 (A Hex) STALL 1110 (E Hex) DATA0 0011 (3 Hex) DATA1 1011 (B Hex) SL811HS Document #: 38-08008 Rev. *A Page 12 of 29 5.2.8 USB-A/USB-B Host Transfer Count Register (Read), USB Address (Write) 04H, 0CH This register has two functions. When read, this register contains the number of bytes left over (from “Length” field) after a packet is transferred. If an overflow condition occurs, i.e., the received packet from slave USB device was greater than the Length field specified, a bit is set in the Packet Status Register indicating the condition. When written, this register will contain the USB Device Address to which the Host wishes to communicate. DA6-DA0 Device address, up to 127 devices can be addressed DA7 Reserved bit should be set zero. 5.3 SL811HS Control Registers 5.3.1 Control Register 1, Address 05H The Control Register 05H enables/disables USB transfer operation with control bits defined as follows. At power-up this register will be cleared to all zeros. In the SL811HS, bit 0 is used to enable HW SOF auto-generation (bit 0 was not used in the SL11H). D7 D6 D5 D4 D3 D2 D1 D0 0 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Register Name SL11H and SL811H SL11H (hex) Address SL811HS (hex) Address Control Register1 05H 05H Interrupt Enable Register 06H 06 H Reserved Register 07H 07 H Status Register 0DH 0DH SOF Counter LOW (Write)/HW Revision Register (Read) 0EH 0E H SOF Counter HIGH and Control Register2 Reserved 0F H Memory Buffer 10H-FFH 10H-FFH Bit Bit Name Function 0 SOF ena/dis “1” enable auto Hardware SOF generation, “0”= disable 1 Reserved 2 Reserved 3 USB Engine Reset USB Engine reset = “1.” Normal set “0” 4 J-K state force See the table below 5 USB Speed “0” set-up for full speed, “1” set-up LOW-SPEED 6 Suspend “1” enable, “0” = disable 7 Reserved SL811HS Document #: 38-08008 Rev. *A Page 13 of 29 5.3.2 J-K Programming States bits 3 and 4 of Control Register 05H The J-K force state control and USB Engine Reset bits can be used to generate USB reset condition on the USB. Forcing K-state can be used for Peripheral device remote wake-up, Resume and other modes. These two bits are set to zero on power-up. 5.3.3 Low-speed/Full Speed Modes bit 5 Control Register 05H The SL811HS is designed to communicate with either full or low-speed devices. At power-up bit 5 will be set LOW, i.e., for full speed. There are two cases when communicating with a low-speed device. When a low-speed device is connected directly to the SL811HS, bit 5 of Register 05H should be set to logic “1” and bit 6 of register 0FH, Output-Invert, needs to be set to “1” in order to change the polarity of D+ and D. When a low-speed device is connected via a HUB to SL811HS, bit 5 of Register 05H should be set to logic “0” and bit 6 of register 0FH should be set to logic “0” in order to keep the polarity of D+ and D for full speed. In addition, make sure that bit 7 of USB-A/USB-B Host Control Registers 00H, 08H is set to “1.” 5.3.4 Low-power Modes bit 6 Control Register 05H When bit-6 (Suspend) is set to “1,” the power of the transmit transceiver will be turned off, the internal RAM will be in the suspend mode, and the internal clocks will be disabled. Note. Any activity on the USB bus (i.e., K-State, etc.) will resume normal operation. To resume normal operation from the CPU side, a data Write cycle (i.e., A0 set HIGH for a data Write cycle) should be done. 5.3.5 Interrupt Enable Register, Address 06H The SL811HS provides an Interrupt Request Output, which can be activated on a number of conditions. The Interrupt Enable Register allows the user to select conditions that will result in an Interrupt being issued to an external CPU. A separate Interrupt Status Register is provided. It can be polled in order to determine those conditions that initiated the interrupt. (See Interrupt Status Register description.) When a bit is set to “1” the corresponding interrupt is enabled. Bits 01 are used for the USB A/B controller interrupt. Bit 4 is used to enable/disable the SOF timer. To utilize this bit function, bit 0 of register 05H must be enabled and the SOF counter registers 0EH and 0FH must be initialized. Bit 5 is used to enable/disable the device inserted/removed interrupt. When bit-6 of register 05H is set = “1,” bit 6 of this register enables the Resume Detect Interrupt. Otherwise, this bit is used to enable Device detection status as defined in the Interrupt Status Register bit definitions. Note: 2. Force K-State for low speed. 3. Force J-State for low speed. Bit 4 Bit 3 Function 0 0 Normal operating mode 0 1 Force USB Reset, D+ and D are set LOW (SE0) 1 0 Force J-State, D+ set HIGH, D set LOW 2 1 1 Force K-State, D set HIGH, D+ set LOW 3 Bit Position Bit Name Function 0 USB-A USB-A Done Interrupt 1 USB-B USB-B Done Interrupt 2 Reserved 3 Reserved 4 SOF Timer 1 = Enable Interrupt on 1-ms SOF Timer 5 Inserted/Removed Slave Insert/Remove Detection 6 Device Detect/Resume Enable Device Detect/Resume Interrupt SL811HS Document #: 38-08008 Rev. *A Page 14 of 29 5.3.6 USB Address Register, Reserved, Address 07H This register is reserved for the device USB Address in Slave operation. It should not be written by the user. 5.3.7 Interrupt Status Register, Address 0DH The ISR is a Read/Write register providing interrupt status. Interrupts can be cleared by writing to this register. To clear a specific interrupt, the register is written with corresponding bit set to “1.” Bit 5 is provided to support USB cable Insertion/Removal for the SL811HS in Host Mode. This bit is set when a transition from SE0 to IDLE (device inserted) or IDLE to SE0 (device removed) occurs on the bus. Bit 6 is shared between Device Detection status and Resume detection interrupt. When bit-6 of register 05H is set to one, this bit will be the Resume detection Interrupt bit. Otherwise, this bit is used to indicate the presence of a Device, “1” = device “Not present” and “0” = device “Present.” In this mode this bit should be checked along with bit 5 to determine whether a device has been inserted or removed. Bit 7 provides continuous USB Data+ line status. Once it has been determined that a device has been inserted as described above with bits 5 and 6, bit 7 can be used to detect if the inserted device is low- or full-speed. 5.3.8 Current Data Set Register/Hardware Revision/SOF Counter LOW, Address 0EH This register has two modes: a Read from this register indicates the current SL811HS silicon revision. Writing to this register will set up auto generation of SOF to all connected peripherals. This counter is based on the 12-MHz clock. To set up a 1-ms timer interval, the software must set up both SOF counter registers to the proper values. Example. To set up SOF for 1-ms interval, SOF counter register 0EH should be set to E0H. Bit Position Bit Name Function 0 USB-A USB-A Done Interrupt 1 USB-B USB-B Done Interrupt 2 Reserved 3 Reserved 4 SOF timer 1 = Interrupt on 1-ms SOF Timer 5 Insert/Remove Slave Insert/Remove Detection 6 Device Detect/Resume Device Detect/Resume Interrupt 7 D+ Value of the Data+ Pin Bit Position Bit Name Function 0 Reserved Reserved for slave 1 Reserved Reserved for slave 2 Reserved Read will be zero 3 Reserved Read will be zero 47 HW Revision SL11H Read = 0H, SL811HS rev1.2 Read = 1H, SL811HS rev1.5 Read = 2 Bit Position Bit Name Function 07 SOF LOW Counter Register Write-only to set SOF LOW Counter Register, OEH SL811HS Document #: 38-08008 Rev. *A Page 15 of 29 5.3.9 SOF Counter HIGH/Control2 Register, Address 0FH, READ/WRITE When writing to this register the bits definition are defined as follows. Note. Any Write to control register 0FH will enable the SL811HS full features bit. This is an internal bit of the SL811HS which enables additional features not supported by the SL11H. For SL11H hardware backward compatibility, this register should not be accessed. The USB-B register set can be used when SL811HS full feature bit is enabled. Example. To set up for 1-ms SOF time: The register 0FH contains the upper 6 bits of the SOF timer. Register 0EH contains the lower 8 bits of the SOF timer. The timer is based on a 12-MHz clock and uses a counter, which counts down to zero from an initial value. To set the timer for 1 ms time, the register 0EH should be loaded with value E0H, register 0F, Bits 05 should be loaded with 2EH. To start the timer, bit 0 of register 05H should be set to “1.” To load both HIGH and LOW registers with the proper values the user must follow this sequence: Write E0H to register 0EH. Write 2EH to register 0FH, bits 05. Bits 6 and 7 should be set for appropriate function: polarity and Master/Slave. Enable bit 0 in register 05H. Note. Any Write to the 0FH register will clear the internal frame counter. Register 0FH must be written