利用EDA技術(shù)設(shè)計(jì)一個(gè)2ASK調(diào)制系統(tǒng)并仿真測(cè)試,利用EDA技術(shù)設(shè)計(jì)一個(gè)2ASK調(diào)制系統(tǒng)并仿真測(cè)試,利用,應(yīng)用,eda,技術(shù)設(shè)計(jì),一個(gè),ask,調(diào)制,系統(tǒng),仿真,測(cè)試 廣西工學(xué)院設(shè)計(jì)報(bào)告專用紙 《通信原理》課程設(shè)計(jì) 說 明 書 設(shè)計(jì)題目 利用EDA技術(shù)設(shè)計(jì)一個(gè)2ASK調(diào)制 系統(tǒng)并仿真測(cè)試 系 別 專業(yè)班級(jí) 學(xué)生姓名 學(xué) 號(hào) 指導(dǎo)教師 日 期 一、前言 2 二、設(shè)計(jì)任務(wù)要求 2 三、2ASK調(diào)制的工作原理 2 1、相乘電路實(shí)現(xiàn)法 3 2、ASK信號(hào)調(diào)制原理 3 四、2ASK信號(hào)產(chǎn)生器 5 1、各部分器件工作原理框圖 5 1）分頻器 5 2）基帶信號(hào)發(fā)生器 7 3）載波信號(hào)發(fā)生器（正弦波發(fā)生器） 9 4） 元件例化 12 2、整體仿真結(jié)果 14 五、 心得體會(huì) 19 六、 參考文獻(xiàn) 19 一、前言 在現(xiàn)代數(shù)字通信系統(tǒng)中，頻帶傳輸系統(tǒng)的應(yīng)用最為突出。將原始的數(shù)字基帶信號(hào)，經(jīng)過頻譜搬移，變換為適合在頻帶上傳輸?shù)念l帶信號(hào)，傳輸這個(gè)信號(hào)的系統(tǒng)就稱為頻帶傳輸系統(tǒng)。在頻帶傳輸系統(tǒng)中，根據(jù)數(shù)字信號(hào)對(duì)載波不同參數(shù)的控制，形成不同的頻帶調(diào)制方法。 當(dāng)選擇正弦波作為載波，用一個(gè)二進(jìn)制基帶信號(hào)對(duì)載波信號(hào)的振幅進(jìn)行調(diào)制時(shí)，產(chǎn)生的信號(hào)就是二進(jìn)制振幅鍵控信號(hào)（2ASK）。例如用電鍵控制一個(gè)載頻振蕩器的輸出，使它時(shí)斷時(shí)續(xù)輸出，這便是一部振幅鍵控的發(fā)報(bào)機(jī)。由于振幅鍵控信號(hào)抗噪聲性能不夠理想，逐步被FSK和PSK代替。但是，作為一種最古老的調(diào)制方式，它還是具有很高的參考價(jià)值。特別是在近幾年隨著對(duì)信息速率要求的提高，要在較窄的頻帶內(nèi)實(shí)現(xiàn)較高信息速率的傳輸，多進(jìn)制的數(shù)字振幅鍵控（MASK）又得到了運(yùn)用，在信道條件較好而頻帶又較緊張的恒參信道中優(yōu)先采用它。下面我們將對(duì)2ASK的調(diào)制系統(tǒng)進(jìn)行討論。 二、設(shè)計(jì)任務(wù)要求 用EDA技術(shù)設(shè)計(jì)一個(gè)2ASK調(diào)制系統(tǒng)并仿真測(cè)試，要求載波頻率為2.2MHZ。 三、2ASK調(diào)制的工作原理 數(shù)字信號(hào)對(duì)載波信號(hào)的振幅調(diào)制稱為振幅鍵控即ASK（Amplitude Shift Keying），2ASK是利用代表數(shù)字信息“0”或“1”的基帶矩形脈沖去鍵控一個(gè)連續(xù)的載波，使載波時(shí)斷時(shí)續(xù)地輸出。有載波輸出時(shí)表示發(fā)送“1”，無載波輸出時(shí)表示發(fā)送“0”。借助幅度調(diào)制的原理，二進(jìn)制振幅鍵控信號(hào)的碼元可以表示為： 式中，為載波角頻率，s(t)為單極性NRZ矩形脈沖序列，即 其中，g(t)是持續(xù)時(shí)間為、高度為1的矩形脈沖，常稱為門函數(shù)；為二進(jìn)制數(shù)字 產(chǎn)生二進(jìn)制振幅鍵控信號(hào)的方法，如圖7-1下所示，注意有兩種：乘法器實(shí)現(xiàn)法和鍵控法。 1、相乘電路實(shí)現(xiàn)法 就是用乘法器基帶信號(hào)S(t）與載波信號(hào)相乘就可以得到調(diào)制信號(hào)輸出。乘法器用來進(jìn)行頻頻搬移，相乘后的信號(hào)通過帶通濾波器濾除高頻諧波和低頻干擾，帶通濾波器的輸出是振幅鍵控信號(hào)。 2、鍵控法 所謂的鍵控法就是一個(gè)開關(guān)電路，但是該開關(guān)電路是由輸入的基帶信號(hào)控制，同樣也可以得到相同的輸出波形。由于振幅鍵控的輸出波形是斷續(xù)的正弦波，所以有些時(shí)候也稱二元制ASK為通斷控制。為了控制開關(guān)電路，基帶信號(hào)必須是矩形脈沖信號(hào)，高電平的時(shí)候，打開開關(guān)，低電平的時(shí)候，隔壁開關(guān)。最典型的實(shí)現(xiàn)方法是用一個(gè)電鍵來控制載波振蕩器的輸出而獲得。 2、ASK信號(hào)調(diào)制原理 在接收端口，ASK信號(hào)的解調(diào)方法有兩種，同步解調(diào)法和包絡(luò)解調(diào)法。前者屬于相干解調(diào)，后者為非相干解調(diào)。圖7-2（a）為包絡(luò)檢波法解調(diào)器的原理方框圖，其中的整流器和低通濾波器構(gòu)成一個(gè)包絡(luò)檢波器。7-（b）為相干解調(diào)器的原理方框圖，由于在相干解調(diào)中相乘電路需要有相干載波，該載波必須從接受信號(hào)中獲取，并且與接受信號(hào)的載波信號(hào)具有相同的頻率以及相同的相位，所以這種方法比包絡(luò)解調(diào)法復(fù)雜。 抽樣判決 帶通濾波 全波整流 低通濾波 S(t） 輸出 （ a ）非相干解調(diào) 抽樣判決器 帶通濾波 相乘電路 低通濾波 S（t） 輸出 （b）相干解調(diào) 圖7-2 ASK信號(hào)解調(diào)原理框圖 ASK隨機(jī)信號(hào)序列的一般表示式為： = 其中，為二進(jìn)制單極性隨機(jī)振幅;g(t)為碼元波形；T為碼元持續(xù)時(shí)間。 其調(diào)制時(shí)間波形如圖下所示： 接收的信號(hào)先通過一個(gè)帶通濾波器，此帶通濾波器的帶寬恰好使信號(hào)的有用頻譜通過并阻止帶外的噪聲通過。設(shè)在一個(gè)碼元持續(xù)時(shí)間T內(nèi)，經(jīng)過帶通濾波器后的接收信號(hào)和噪聲電壓為： Y（t）=s(t)+n(t) 0'0'); CLK_temp <=NOT CLK_temp; ELSE count <= count +1; END IF ; END IF ; END PROCESS; CLK_100 <= CLK_temp; END div_100; 仿真圖如下所示： 2）基帶信號(hào)發(fā)生器 ．m序列產(chǎn)生器 m序列是偽隨機(jī)序列的一種，它的顯著特點(diǎn)是：隨機(jī)特性，預(yù)先可確定性，循環(huán)特性。正因?yàn)檫@些特性，使得m序列產(chǎn)生器在通信領(lǐng)域得到了廣泛的應(yīng)用。本例用一種帶有兩個(gè)反饋抽頭的3級(jí)反饋移位寄存器，得到一串“1110010”循環(huán)序列，并采取措施防止進(jìn)入全“0”狀態(tài)。通過更換時(shí)鐘頻率可以方便地改變輸入碼元的速率。m序列產(chǎn)生器的電路結(jié)構(gòu)如圖7-4所示。 7-4 M序列產(chǎn)生器 跳變檢測(cè) 將跳變檢測(cè)引入正弦波的產(chǎn)生中，可以使每次基帶碼元上升沿或下降沿到來時(shí)，對(duì)應(yīng)輸出波形位于正弦波形的sin0處。引入跳變檢測(cè)主要是為了便于觀察，確保示波器上顯示為一個(gè)連續(xù)的波形?；鶐盘?hào)的跳變檢測(cè)可以有很多方法，圖7-5為一種便于在可編程邏輯器件中實(shí)現(xiàn)的方案。 7-5 信號(hào)跳變電路 序列輸出 輸入時(shí)鐘 計(jì)數(shù)器 基帶信號(hào)發(fā)生器工作原理： 消除毛刺 復(fù)位CLR 當(dāng)有時(shí)鐘信號(hào)時(shí)，計(jì)數(shù)器計(jì)數(shù)一次，如此便產(chǎn)生了所需要的基帶信號(hào)。當(dāng)有復(fù)位信號(hào)時(shí)，計(jì)數(shù)重新開始計(jì)數(shù)，重新輸出所需要的序列。 基帶信號(hào)發(fā)生器VHDL描述如下： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY xulie IS PORT(CLK0,CLR:IN STD_LOGIC; Q0:OUT STD_LOGIC); END xulie; ARCHITECTURE one OF xulie IS SIGNAL COUNT: STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL Z:STD_LOGIC :='0'; BEGIN PROCESS(CLK0,CLR) BEGIN IF(CLR='1')THEN COUNT<="000"; ELSE IF(CLK0='1'AND CLK0'EVENT)THEN IF(COUNT="111")THEN COUNT<="000"; ELSE COUNT<=COUNT +'1'; END IF; END IF; END IF; END PROCESS; PROCESS(COUNT) BEGIN CASE COUNT IS WHEN "000"=>Z<='0'; WHEN "001"=>Z<='1'; WHEN "010"=>Z<='0'; WHEN "011"=>Z<='1'; WHEN "100"=>Z<='0'; WHEN "101"=>Z<='0'; WHEN "110"=>Z<='1'; WHEN OTHERS=>Z<='0'; END CASE; END PROCESS; PROCESS(CLK0,Z) BEGIN --消除毛刺的鎖存器 IF(CLK0'EVENT AND CLK0='1')THEN Q0<=Z; END IF; END PROCESS; END one; 仿真圖如下： 3）載波信號(hào)發(fā)生器（正弦波發(fā)生器） 用數(shù)字電路和DAC變換器可以產(chǎn)生要求的模擬信號(hào)。根據(jù)抽樣定理可知，當(dāng)用模擬信號(hào)最大頻率兩倍以上的速率對(duì)該模擬信號(hào)采樣時(shí)，便可將原模擬信號(hào)不失真地恢復(fù)出來。本例要求得到的是兩個(gè)不同頻率的正弦信號(hào)，實(shí)驗(yàn)中對(duì)正弦波每個(gè)周期采樣100個(gè)點(diǎn)，即采樣速率為原正弦信號(hào)頻率的100倍，因此完全可以在接收端將原正弦信號(hào)不失真地恢復(fù)出來，從而可以在接收端對(duì)ASK信號(hào)正確地解調(diào)。經(jīng)DAC轉(zhuǎn)換后，可以在示波器上觀察到比較理想的波形。本實(shí)驗(yàn)中每個(gè)采樣點(diǎn)采用8位量化編碼，即8位分辨率。采樣點(diǎn)的個(gè)數(shù)與分辨率的大小主要取決于CPLD/FPGA器件的容量，其中分辨率的高低還與DAC的位數(shù)有關(guān)。實(shí)驗(yàn)表明，采用8位分辨率和每周期100個(gè)采樣點(diǎn)可以達(dá)到相當(dāng)不錯(cuò)的效果。具體的正弦信號(hào)產(chǎn)生器可以用狀態(tài)機(jī)來實(shí)現(xiàn)。按前面的設(shè)計(jì)思路，本實(shí)現(xiàn)方案共需100個(gè)狀態(tài)，分別為s1～s100。同時(shí)設(shè)計(jì)一個(gè)異步復(fù)位端，保證當(dāng)每個(gè)“1”或“0”到來時(shí)其調(diào)制信號(hào)正好位于坐標(biāo)原點(diǎn)，即sin0處。狀態(tài)機(jī)共有8位輸出(Q7～Q0)，經(jīng)DAC變換為模擬信號(hào)輸出。為得到一個(gè)純正弦波形，應(yīng)在DAC的輸出端加上一個(gè)低通濾波器，由于本例僅觀察ASK信號(hào)，因此省去了低通濾波器。本設(shè)計(jì)中，數(shù)字基帶信號(hào)與ASK調(diào)制信號(hào)的對(duì)應(yīng)關(guān)系為“0”對(duì)應(yīng)0，“1”對(duì)應(yīng)2.2MHz，此二載波的頻率可以方便地通過軟件修改。 程序代碼： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CLK1 IS PORT( CLOCK: IN STD_LOGIC; CODE: IN STD_LOGIC; data: out std_logic_vector (7 DOWNTO 0) ); END CLK1 ; ARCHITECTURE CLK_ARCH OF CLK1 IS SIGNAL DOUT:std_logic_vector (7 DOWNTO 0); --正弦波數(shù)據(jù) SIGNAL countda:std_logic_vector (6 DOWNTO 0);--波形數(shù)據(jù)查表地址 BEGIN PROCESS(clock) BEGIN IF ( clock'EVENT AND clock= '1') THEN IF (CODE='0') then countda<="0000000"; ELSIF( countda="1100011" and CODE='1') then countda<="0000000"; else countda<=countda+'1'; END IF; END IF; END PROCESS; PROCESS(countda) BEGIN CASE countda IS WHEN "0000000" =>DOUT<= "01111111"; WHEN "0000001" =>DOUT<= "10000111"; WHEN "0000010" =>DOUT<= "10001111"; WHEN "0000011" =>DOUT<= "10010111"; WHEN "0000100" =>DOUT<= "10011111"; WHEN "0000101" =>DOUT<= "10100110"; WHEN "0000110" =>DOUT<= "10101110"; WHEN "0000111" =>DOUT<= "10110101"; WHEN "0001000" =>DOUT<= "10111100"; WHEN "0001001" =>DOUT<= "11000011"; WHEN "0001010" =>DOUT<= "11001010"; WHEN "0001011" =>DOUT<= "11010000"; WHEN "0001100" =>DOUT<= "11010110"; WHEN "0001101" =>DOUT<= "11011100"; WHEN "0001110" =>DOUT<= "11100001"; WHEN "0001111" =>DOUT<= "11100110"; WHEN "0010000" =>DOUT<= "11101011"; WHEN "0010001" =>DOUT<= "11101111"; WHEN "0010010" =>DOUT<= "11110010"; WHEN "0010011" =>DOUT<= "11110110"; WHEN "0010100" =>DOUT<= "11111000"; WHEN "0010101" =>DOUT<= "11111010"; WHEN "0010110" =>DOUT<= "11111100"; WHEN "0010111" =>DOUT<= "11111101"; WHEN "0011000" =>DOUT<= "11111110"; WHEN "0011001" =>DOUT<= "11111111"; WHEN "0011010" =>DOUT<= "11111110"; WHEN "0011011" =>DOUT<= "11111101"; WHEN "0011100" =>DOUT<= "11111100"; WHEN "0011101" =>DOUT<= "11111010"; WHEN "0011110" =>DOUT<= "11111000"; WHEN "0011111" =>DOUT<= "11110110"; WHEN "0100000" =>DOUT<= "11110010"; WHEN "0100001" =>DOUT<= "11101111"; WHEN "0100010" =>DOUT<= "11101011"; WHEN "0100011" =>DOUT<= "11100110"; WHEN "0100100" =>DOUT<= "11100001"; WHEN "0100101" =>DOUT<= "11011100"; WHEN "0100110" =>DOUT<= "11010110"; WHEN "0100111" =>DOUT<= "11010000"; WHEN "0101000" =>DOUT<= "11001010"; WHEN "0101001" =>DOUT<= "11000011"; WHEN "0101010" =>DOUT<= "10111100"; WHEN "0101011" =>DOUT<= "10110101"; WHEN "0101100" =>DOUT<= "10101110"; WHEN "0101101" =>DOUT<= "10100110"; WHEN "0101110" =>DOUT<= "10011111"; WHEN "0101111" =>DOUT<= "10010111"; WHEN "0110000" =>DOUT<= "10001111"; WHEN "0110001" =>DOUT<= "10000111"; WHEN "0110010" =>DOUT<= "01111111"; WHEN "0110011" =>DOUT<= "01110111"; WHEN "0110100" =>DOUT<= "01101111"; WHEN "0110101" =>DOUT<= "01100111"; WHEN "0110110" =>DOUT<= "01011111"; WHEN "0110111" =>DOUT<= "01011000"; WHEN "0111000" =>DOUT<= "01010000"; WHEN "0111001" =>DOUT<= "01001001"; WHEN "0111010" =>DOUT<= "01000010"; WHEN "0111011" =>DOUT<= "00111011"; WHEN "0111100" =>DOUT<= "00110100"; WHEN "0111101" =>DOUT<= "00101110"; WHEN "0111110" =>DOUT<= "00101000"; WHEN "0111111" =>DOUT<= "00100010"; WHEN "1000000" =>DOUT<= "00011101"; WHEN "1000001" =>DOUT<= "00011000"; WHEN "1000010" =>DOUT<= "00010011"; WHEN "1000011" =>DOUT<= "00001111"; WHEN "1000100" =>DOUT<= "00001100"; WHEN "1000101" =>DOUT<= "00001000"; WHEN "1000110" =>DOUT<= "00000110"; WHEN "1000111" =>DOUT<= "00000100"; WHEN "1001000" =>DOUT<= "00000010"; WHEN "1001001" =>DOUT<= "00000001"; WHEN "1001010" =>DOUT<= "00000000"; WHEN "1001011" =>DOUT<= "00000000"; WHEN "1001100" =>DOUT<= "00000000"; WHEN "1001101" =>DOUT<= "00000001"; WHEN "1001110" =>DOUT<= "00000010"; WHEN "1001111" =>DOUT<= "00000100"; WHEN "1010000" =>DOUT<= "00000110"; WHEN "1010001" =>DOUT<= "00001000"; WHEN "1010010" =>DOUT<= "00001100"; WHEN "1010011" =>DOUT<= "00001111"; WHEN "1010100" =>DOUT<= "00010011"; WHEN "1010101" =>DOUT<= "00011000"; WHEN "1010110" =>DOUT<= "00011101"; WHEN "1010111" =>DOUT<= "00100010"; WHEN "1011000" =>DOUT<= "00101000"; WHEN "1011001" =>DOUT<= "00101110"; WHEN "1011010" =>DOUT<= "00110100"; WHEN "1011011" =>DOUT<= "00111011"; WHEN "1011100" =>DOUT<= "01000010"; WHEN "1011101" =>DOUT<= "01001001"; WHEN "1011110" =>DOUT<= "01010000"; WHEN "1011111" =>DOUT<= "01011000"; WHEN "1100000" =>DOUT<= "01011111"; WHEN "1100001" =>DOUT<= "01100111"; WHEN "1100010" =>DOUT<= "01101111"; WHEN "1100011" =>DOUT<= "01110111"; when others=>NULL; END CASE; END PROCESS; data<=DOUT; END CLK_ARCH; 仿真圖如下所示： 4） 元件例化 元件例化外部結(jié)構(gòu)圖如下所示： CLK data1 START 程序代碼： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; ENTITY lihua IS PORT(CLK:IN STD_LOGIC; START:IN STD_LOGIC; data1:out std_logic_vector (7 DOWNTO 0)); END lihua; ARCHITECTURE one_lihua OF lihua IS COMPONENT CLKDIV PORT(CLK: IN STD_LOGIC; CLK_100: OUT STD_LOGIC); END COMPONENT CLKDIV; COMPONENT xulie PORT(CLK0,CLR:IN STD_LOGIC; Q0:OUT STD_LOGIC); END COMPONENT xulie; COMPONENT CLK1 PORT( CLOCK: IN STD_LOGIC; CODE: IN STD_LOGIC; data: out std_logic_vector (7 DOWNTO 0) ); END COMPONENT CLK1; SIGNAL temp1,temp2:STD_LOGIC; BEGIN U1:CLKDIV PORT MAP (CLK,temp1); U2:xulie PORT MAP (temp1,START,temp2); U3:CLK1 PORT MAP (CLK,temp2,data1); END ARCHITECTURE one_lihua; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; ENTITY lihua IS PORT(CLK:IN STD_LOGIC; START:IN STD_LOGIC; DATA1:out std_logic_vector (7 DOWNTO 0)); END lihua; ARCHITECTURE one_lihua OF lihua IS COMPONENT CLKDIV PORT(CLK: IN STD_LOGIC; CLK_100: OUT STD_LOGIC); END COMPONENT CLKDIV; COMPONENT xulie PORT(CLK0,CLR:IN STD_LOGIC; Q0:OUT STD_LOGIC); END COMPONENT xulie; COMPONENT CLK1 PORT( CLOCK: IN STD_LOGIC; CODE: IN STD_LOGIC; data: out std_logic_vector (7 DOWNTO 0) ); END COMPONENT CLK1; SIGNAL temp1,temp2:STD_LOGIC; BEGIN U1:CLKDIV PORT MAP (CLK,temp1); U2:xulie PORT MAP (temp1,START,temp2); U3:CLK1 PORT MAP (CLK,temp2,DATA1); END ARCHITECTURE one_lihua; 2、整體仿真結(jié)果 把以上的幾個(gè)程序合起來，就是實(shí)現(xiàn)2ASK調(diào)制信號(hào)的總程序 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CLKDIV IS PORT(CLK : IN STD_LOGIC; CLK_100 : OUT STD_LOGIC); END CLKDIV; ARCHITECTURE div_100 OF CLKDIV IS SIGNAL count : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL CLK_temp : STD_LOGIC; BEGIN PROCESS(CLK) BEGIN IF (CLK 'event AND CLK='1') THEN IF(count="00110010") THEN count <= (OTHERS =>'0'); CLK_temp <=NOT CLK_temp; ELSE count <= count +1; END IF ; END IF ; END PROCESS; CLK_100 <= CLK_temp; END div_100; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY xulie IS PORT(CLK0,CLR:IN STD_LOGIC; Q0:OUT STD_LOGIC); END xulie; ARCHITECTURE one OF xulie IS SIGNAL COUNT: STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL Z:STD_LOGIC :='0'; BEGIN PROCESS(CLK0,CLR) BEGIN IF(CLR='1')THEN COUNT<="000"; ELSE IF(CLK0='1'AND CLK0'EVENT)THEN IF(COUNT="111")THEN COUNT<="000"; ELSE COUNT<=COUNT +'1'; END IF; END IF; END IF; END PROCESS; PROCESS(COUNT) BEGIN CASE COUNT IS WHEN "000"=>Z<='0'; WHEN "001"=>Z<='1'; WHEN "010"=>Z<='0'; WHEN "011"=>Z<='1'; WHEN "100"=>Z<='0'; WHEN "101"=>Z<='0'; WHEN "110"=>Z<='1'; WHEN OTHERS=>Z<='0'; END CASE; END PROCESS; PROCESS(CLK0,Z) BEGIN --消除毛刺的鎖存器 IF(CLK0'EVENT AND CLK0='1')THEN Q0<=Z; END IF; END PROCESS; END one; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CLK1 IS PORT( CLOCK: IN STD_LOGIC; CODE: IN STD_LOGIC; data: out std_logic_vector (7 DOWNTO 0) ); END CLK1 ; ARCHITECTURE CLK_ARCH OF CLK1 IS SIGNAL DOUT:std_logic_vector (7 DOWNTO 0); --正弦波數(shù)據(jù) SIGNAL countda:std_logic_vector (6 DOWNTO 0);--波形數(shù)據(jù)查表地址 BEGIN PROCESS(clock) BEGIN IF ( clock'EVENT AND clock= '1') THEN IF (CODE='0') then countda<="0000000"; ELSIF( countda="1100011" and CODE='1') then countda<="0000000"; else countda<=countda+'1'; END IF; END IF; END PROCESS; PROCESS(countda) BEGIN CASE countda IS WHEN "0000000" =>DOUT<= "01111111"; WHEN "0000001" =>DOUT<= "10000111"; WHEN "0000010" =>DOUT<= "10001111"; WHEN "0000011" =>DOUT<= "10010111"; WHEN "0000100" =>DOUT<= "10011111"; WHEN "0000101" =>DOUT<= "10100110"; WHEN "0000110" =>DOUT<= "10101110"; WHEN "0000111" =>DOUT<= "10110101"; WHEN "0001000" =>DOUT<= "10111100"; WHEN "0001001" =>DOUT<= "11000011"; WHEN "0001010" =>DOUT<= "11001010"; WHEN "0001011" =>DOUT<= "11010000"; WHEN "0001100" =>DOUT<= "11010110"; WHEN "0001101" =>DOUT<= "11011100"; WHEN "0001110" =>DOUT<= "11100001"; WHEN "0001111" =>DOUT<= "11100110"; WHEN "0010000" =>DOUT<= "11101011"; WHEN "0010001" =>DOUT<= "11101111"; WHEN "0010010" =>DOUT<= "11110010"; WHEN "0010011" =>DOUT<= "11110110"; WHEN "0010100" =>DOUT<= "11111000"; WHEN "0010101" =>DOUT<= "11111010"; WHEN "0010110" =>DOUT<= "11111100"; WHEN "0010111" =>DOUT<= "11111101"; WHEN "0011000" =>DOUT<= "11111110"; WHEN "0011001" =>DOUT<= "11111111"; WHEN "0011010" =>DOUT<= "11111110"; WHEN "0011011" =>DOUT<= "11111101"; WHEN "0011100" =>DOUT<= "11111100"; WHEN "0011101" =>DOUT<= "11111010"; WHEN "0011110" =>DOUT<= "11111000"; WHEN "0011111" =>DOUT<= "11110110"; WHEN "0100000" =>DOUT<= "11110010"; WHEN "0100001" =>DOUT<= "11101111"; WHEN "0100010" =>DOUT<= "11101011"; WHEN "0100011" =>DOUT<= "11100110"; WHEN "0100100" =>DOUT<= "11100001"; WHEN "0100101" =>DOUT<= "11011100"; WHEN "0100110" =>DOUT<= "11010110"; WHEN "0100111" =>DOUT<= "11010000"; WHEN "0101000" =>DOUT<= "11001010"; WHEN "0101001" =>DOUT<= "11000011"; WHEN "0101010" =>DOUT<= "10111100"; WHEN "0101011" =>DOUT<= "10110101"; WHEN "0101100" =>DOUT<= "10101110"; WHEN "0101101" =>DOUT<= "10100110"; WHEN "0101110" =>DOUT<= "10011111"; WHEN "0101111" =>DOUT<= "10010111"; WHEN "0110000" =>DOUT<= "10001111"; WHEN "0110001" =>DOUT<= "10000111"; WHEN "0110010" =>DOUT<= "01111111"; WHEN "0110011" =>DOUT<= "01110111"; WHEN "0110100" =>DOUT<= "01101111"; WHEN "0110101" =>DOUT<= "01100111"; WHEN "0110110" =>DOUT<= "01011111"; WHEN "0110111" =>DOUT<= "01011000"; WHEN "0111000" =>DOUT<= "01010000"; WHEN "0111001" =>DOUT<= "01001001"; WHEN "0111010" =>DOUT<= "01000010"; WHEN "0111011" =>DOUT<= "00111011"; WHEN "0111100" =>DOUT<= "00110100"; WHEN "0111101" =>DOUT<= "00101110"; WHEN "0111110" =>DOUT<= "00101000"; WHEN "0111111" =>DOUT<= "00100010"; WHEN "1000000" =>DOUT<= "00011101"; WHEN "1000001" =>DOUT<= "00011000"; WHEN "1000010" =>DOUT<= "00010011"; WHEN "1000011" =>DOUT<= "00001111"; WHEN "1000100" =>DOUT<= "00001100"; WHEN "1000101" =>DOUT<= "00001000"; WHEN "1000110" =>DOUT<= "00000110"; WHEN "1000111" =>DOUT<= "00000100"; WHEN "1001000" =>DOUT<= "00000010"; WHEN "1001001" =>DOUT<= "00000001"; WHEN "1001010" =>DOUT<= "00000000"; WHEN "1001011" =>DOUT<= "00000000"; WHEN "1001100" =>DOUT<= "00000000"; WHEN "1001101" =>DOUT<= "00000001"; WHEN "1001110" =>DOUT<= "00000010"; WHEN "1001111" =>DOUT<= "00000100"; WHEN "1010000" =>DOUT<= "00000110"; WHEN "1010001" =>DOUT<= "00001000"; WHEN "1010010" =>DOUT<= "00001100"; WHEN "1010011" =>DOUT<= "00001111"; WHEN "1010100" =>DOUT<= "00010011"; WHEN "1010101" =>DOUT<= "00011000"; WHEN "1010110" =>DOUT<= "00011101"; WHEN "1010111" =>DOUT<= "00100010"; WHEN "1011000" =>DOUT<= "00101000"; WHEN "1011001" =>DOUT<= "00101110"; WHEN "1011010" =>DOUT<= "00110100"; WHEN "1011011" =>DOUT<= "00111011"; WHEN "1011100" =>DOUT<= "01000010"; WHEN "1011101" =>DOUT<= "01001001"; WHEN "1011110" =>DOUT<= "01010000"; WHEN "1011111" =>DOUT<= "01011000"; WHEN "1100000" =>DOUT<= "01011111"; WHEN "1100001" =>DOUT<= "01100111"; WHEN "1100010" =>DOUT<= "01101111"; WHEN "1100011" =>DOUT<= "01110111"; when others=>NULL; END CASE; END PROCESS; data<=DOUT; END CLK_ARCH; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; ENTITY lihua IS PORT(CLK:IN STD_LOGIC; START:IN STD_LOGIC; data1:out std_logic_vector (7 DOWNTO 0)); END lihua; ARCHITECTURE one_lihua OF lihua IS COMPONENT CLKDIV PORT(CLK: IN STD_LOGIC; CLK_100: OUT STD_LOGIC); END COMPONENT CLKDIV; COMPONENT xulie PORT(CLK0,CLR:IN STD_LOGIC; Q0:OUT STD_LOGIC); END COMPONENT xulie; COMPONENT CLK1 PORT( CLOCK: IN STD_LOGIC; CODE: IN STD_LOGIC; data: out std_logic_vector (7 DOWNTO 0) ); END COMPONENT CLK1; SIGNAL temp1,temp2:STD_LOGIC; BEGIN U