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Intelligent traffic light
With economic development, increased the number of vehicles, road congestion is becoming increasingly serious, intelligent traffic lights on the emerged. At present, the world's Intelligent Transportation System will be: a huge structure, management difficulties, such as the maintenance of large inputs. In order to improve the existing traffic conditions, and to overcome the existing shortcomings of intelligent transportation system I designed analog control traffic lights in urban and rural areas of small-scale smart traffic lights. It has small size, intelligence, maintenance into small, easy to install and so on. And other intelligent transportation system compared to the system to adapt to economic and social development, in line with the current status of scientific and technological development.
Intelligent traffic lights are a comprehensive use of computer network communication technology, sensor technology to manage the automatic control system of traffic lights. Urban traffic control system is used for urban traffic data monitoring, traffic signal control and traffic management computer system; it is the modern urban traffic control system command and the most important component. In short, how to use the appropriate control method to maximize the use of costly cities to build high-speed roads, trunk road and the ramp to alleviate urban areas with the neighboring state of traffic congestion has become more and more traffic management and urban planning departments need to address the main problem. To this end, this article on the urban traffic light control system analog circuit theory, design calculation and experimental testing and other issues to discuss specific analysis.
The General Situation of AT89C51
Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Platform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of this environment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.
1.1 Introduction
The 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financially prohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components are extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions. This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully. Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts. The type of the device and its application requirements determine which types of testing are performed on the device.
1.2 The AT89C51 provides the following standard features:
4Kbytes of flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.
1.3Pin Description
GND Ground.
Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs .Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull-ups are required during program verification.
Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 1 also receives the low-order address bytes during Flash programming and verification.
Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses . In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 also serves the functions of various special feature soft the AT89C51 as listed below:
RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.
ALE/PROG：Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
PSEN：Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin all receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.
Chip erase
The power to erase the entire Flash array, through the appropriate combination of control signals and by holding ALE / 10 ms compiled low. "1" written in code array chip erase operation must be performed before the code memory can be reprogrammed. Byte of each code in the flash memory array can be written, and the entire array can be erased through the appropriate combination of control signals. Write cycle is self-timed, and once started, will be automatically done. Information between the computer interface into a computer electronic system to process the information outside the two forms. There is a physical signal, it represents the value of the plan. Any interface functions can be divided into the number of operations that modify data in some way, the conversion process between the internal and external form of a number of steps. Analog – digital converter for continuously variable signals into digital form, may be taken by a fixed binary value. If the discontinuous change in the output of the sensor, there is no ADC is necessary. In this case, the signal conditioning section must input signals into a direct connection to the part of the form next to the interface, input / output section of the output interface of the computer itself, takes a similar form, the obvious difference is that the information the flow in the opposite direction, it is through to the outside world, in this case, the program may call an output routine supervision and operator interface, and implementation ratio can be used for digital - analog converter digital . This subroutine in turn pass the information generated, it can be converted into a corresponding electrical signal output device using the DAC analog form. In the form of operating conditions of the last signal for the implementing agency. Almost always used in the microcomputer circuit signal is too small to connect directly to the outside world, you must use some kind of interface translation . they are a more appropriate form of interface circuit part of the design we have seen computer engineers who wish to apply for one of the most important task facing the form of this figure is only the most useful computer connected to the device can be turned on or off, in a discrete bit mode of the micro-computer, where each bit represents a switch or regulator in order to resolve the status of real-world problems, the microcontroller must be more than just a CPU, a program and data memory. in addition, it must include the hardware to allow the CPU to access information from the outside world. Once the CPU to gather information and processing data must be able to change on the outside of some parts of these hardware devices, peripherals, CPU outside the window.
The peripheral micro-controller provides the most basic form is a general-purpose I70ports, each I /O pins can be used as input or output. The function of each pin is set or clear the corresponding bit data direction register in the appropriate decisions in the initialization phase of the program, each output pin to drive the CPU instructions used by the pin can be considered to use the program instructions the CPU (or read). Some type of logic 1 or logic 0. Communication function of the serial unit includes a Microcontroller , CPU and external devices to communicate serial format, instead of using bit parallel format and require less I / O pins, which makes it cheaper, but slower The serial transmission synchronous or asynchronous
黃河科技學(xué)院畢業(yè)設(shè)計(jì)（文獻(xiàn)翻譯） 第 5 頁(yè)
智能交通燈簡(jiǎn)述
隨著經(jīng)濟(jì)的發(fā)展，車輛的數(shù)目不斷增加，道路堵車現(xiàn)象日益嚴(yán)重，智能交通燈就應(yīng)運(yùn)而生了。目前世界上的智能交通系統(tǒng)存在的問題是：系統(tǒng)結(jié)構(gòu)龐大、管理困難、維護(hù)投入大等。為了改善現(xiàn)有的交通狀況，并克服現(xiàn)有智能交通系統(tǒng)的缺點(diǎn)我設(shè)計(jì)了城鄉(xiāng)交通燈模擬控制小型化的智能交通燈。它具有小型化、智能化、維修投入小、易于安裝等特點(diǎn)。與其他的智能交通系統(tǒng)相比該系統(tǒng)更適應(yīng)經(jīng)濟(jì)和社會(huì)的發(fā)展，符合目前科技發(fā)展的現(xiàn)狀。
智能交通燈是一項(xiàng)綜合運(yùn)用網(wǎng)絡(luò)通訊計(jì)算機(jī)技術(shù)、感應(yīng)技術(shù)來管理交通燈具的自動(dòng)控制系統(tǒng)。城市交通控制系統(tǒng)是用于城市交通數(shù)據(jù)監(jiān)測(cè)、交通信號(hào)燈控制與交通疏導(dǎo)的計(jì)算機(jī)綜合管理系統(tǒng)，它是現(xiàn)代城市交通監(jiān)控指揮系統(tǒng)中最重要的組成部分?？傊?，如何采用合適的控制方法，最大限度利用好耗費(fèi)巨資修建的城市高速道路，緩解主干道與坡道、城區(qū)同周邊地區(qū)的交通擁堵狀況，越來越成為交通運(yùn)輸管理和城市規(guī)劃部門亟待解決的主要問題。為此，本文就城鄉(xiāng)交通燈模擬控制系統(tǒng)的電路原理、設(shè)計(jì)計(jì)算和實(shí)驗(yàn)調(diào)試等問題來進(jìn)行具體分析討論。
AT89C51
AT89C51概況
單片機(jī)控制器被用來在眾多的商業(yè)應(yīng)用，如調(diào)制解調(diào)器，電機(jī)控制系統(tǒng)，空調(diào)控制系統(tǒng)，汽車發(fā)動(dòng)機(jī)和其他領(lǐng)域。高處理速度和增強(qiáng)型微控制器的外設(shè)集，使它們適合這樣高速的基于事件的應(yīng)用程序。然而，這些關(guān)鍵的應(yīng)用領(lǐng)域也需要這些單片機(jī)控制器性能是高度可靠的?？纱_保高可靠性和低市場(chǎng)風(fēng)險(xiǎn)由一個(gè)強(qiáng)大的測(cè)試過程和一個(gè)適當(dāng)?shù)墓ぞ撸瑸檫@些微控制器在組件和系統(tǒng)級(jí)驗(yàn)證環(huán)境。 Intel平臺(tái)工程部門開發(fā)驗(yàn)證它的AT89C51的汽車微控制器面向?qū)ο蠖嗑€程的測(cè)試環(huán)境。這種環(huán)境下的不僅為AT89C51的汽車微控制器提供一個(gè)寬廣的測(cè)試環(huán)境，而且發(fā)展的環(huán)境可以很容易地?cái)U(kuò)展和其他幾個(gè)未來的微控制器的驗(yàn)證重用。環(huán)境與Microsoft基礎(chǔ)類（AT89C51）為共同發(fā)展。本文介紹了本次測(cè)試環(huán)境的設(shè)計(jì)和機(jī)制，與各種軟/硬件環(huán)境組成部分的相互作用，以及如何使用AT89C51的。
MCS - 51簡(jiǎn)介
8位單片機(jī)AT89C51?CHMOS微控制器的設(shè)計(jì)用于處理高速計(jì)算和快速輸入/輸出的操作。MCS - 51單片機(jī)通常用于高速事件控制系統(tǒng)。商業(yè)應(yīng)用包括調(diào)制解調(diào)器，電機(jī)控制系統(tǒng)，打印機(jī)，復(fù)印機(jī)，空調(diào)控制系統(tǒng)，磁盤驅(qū)動(dòng)器，醫(yī)療器械。汽車行業(yè)使用MCS 51單片機(jī)在發(fā)動(dòng)機(jī)控制系統(tǒng)，安全氣囊，懸架系統(tǒng)，防抱死制動(dòng)系統(tǒng)（ABS）。 AT89C51從效益上特別適合于應(yīng)用程序，其處理速度和增強(qiáng)型外設(shè)功能，如在汽車動(dòng)力傳動(dòng)控制，車輛動(dòng)態(tài)懸架，防抱死制動(dòng)，穩(wěn)定控制系統(tǒng)的應(yīng)用。因?yàn)檫@些關(guān)鍵的應(yīng)用，市場(chǎng)需要一個(gè)可靠的成本低的中斷延遲響應(yīng)，服務(wù)能力大的需要驅(qū)動(dòng)時(shí)間和事件在實(shí)時(shí)應(yīng)用中的集成外設(shè)，以及一個(gè)高于平均處理能力水平的CPU控制器的軟件包。設(shè)備操作的財(cái)務(wù)和法律風(fēng)險(xiǎn)是很難預(yù)測(cè)的。一旦在市場(chǎng)上，尤其是在關(guān)鍵任務(wù)應(yīng)用，如自動(dòng)駕駛儀或防抱死制動(dòng)系統(tǒng)的失誤將使財(cái)政望而卻步。為50萬美元的設(shè)計(jì)成本可以運(yùn)行高得多，如果修復(fù)意味著2回注釋整個(gè)產(chǎn)品系列共享相同的核心和/或外圍設(shè)備的設(shè)計(jì)缺陷。此外，更換零部件領(lǐng)域是極其昂貴的，因?yàn)檫@些設(shè)備通常是密封模塊組件的幾次，總價(jià)值。為了減輕這些問題，單片機(jī)控制器是必不可少的，同時(shí)在最壞情況下的環(huán)境和電壓條件下的組件級(jí)和系統(tǒng)級(jí)進(jìn)行全面的測(cè)試控制器。這種全面，徹底的驗(yàn)證，不僅需要一個(gè)定義良好的過程，也需要一個(gè)適當(dāng)?shù)沫h(huán)境和工具，以方便和成功地執(zhí)行任務(wù)。英特爾錢德勒平臺(tái)工程組提供各種微控制器和處理器后硅系統(tǒng)驗(yàn)證（SV）。系統(tǒng)驗(yàn)證過程可分為三個(gè)主要部分。設(shè)備的類型及其應(yīng)用的要求，確定在哪些類型的測(cè)試設(shè)備上進(jìn)行。窗體頂端
AT89C51提供以下標(biāo)準(zhǔn)功能：
4KB的閃存，128字節(jié)RAM，32 條I / O線，兩個(gè)16位的定時(shí)器/計(jì)數(shù)器，一個(gè)兩級(jí)五向量中斷結(jié)構(gòu)，一個(gè)完整的全雙工串行口，片上振蕩器和時(shí)鐘電路。此外，AT89C51的靜態(tài)邏輯運(yùn)行可下降到零頻率，并支持兩種軟件可選的節(jié)電模式?？臻e模式時(shí)CPU停止工作，同時(shí)允許的RAM，定時(shí)器/計(jì)數(shù)器，串口和中斷系統(tǒng)繼續(xù)運(yùn)行。掉電模式保存RAM的內(nèi)容，但凍結(jié)振蕩器，禁用所有其他芯片功能，直到下一次硬件復(fù)位。
1-3引腳描述
VCC電源電壓。
GND接地。
端口0：端口0是一個(gè)8位漏極開路雙向I / O端口。作為一個(gè)輸出端口，每個(gè)引腳可以驅(qū)動(dòng)8個(gè)TTL輸入。當(dāng)1寫入端口0引腳，引腳可以用作高阻抗輸入，為了在訪問外部程序和數(shù)據(jù)存儲(chǔ)器的地址/數(shù)據(jù)總線，這種模式下P0具有內(nèi)部上拉電阻，端口0也可以被配置為低8位地址使用。端口0接收FLASH編程的代碼字節(jié)期間，方案論證過程中輸出代碼字節(jié)。外部上拉的過程中需要核查程序。
端口1：端口1是一個(gè)8位雙向內(nèi)部上拉I / O端口。端口1的輸出緩沖器可以吸收來自四個(gè)TTL的輸入。當(dāng)1寫入端口1他們會(huì)被內(nèi)部上拉拉高，并可以用作輸入引腳。端口1，被外部拉低，因?yàn)榈蛯?huì)使電流源（IIL）引腳內(nèi)部上拉。端口1還可以接收低地址字節(jié)的flash編程和校驗(yàn)。
端口2：端口2是一個(gè)8位雙向內(nèi)部上拉I / O的端口。端口2輸出緩沖器可以吸收來自四個(gè)TTL的輸入。當(dāng)1寫入端口2他們會(huì)被內(nèi)部上拉拉高，并可以用作輸入引腳。作為輸入，端口2引腳在外部被拉低將源電流（IIL）由于內(nèi)部上拉。端口2發(fā)出的高階地址字節(jié)在從外部程序存儲(chǔ)器獲取和訪問端口2引腳被外部拉低時(shí)，低源電流（IIL）由于內(nèi)部上拉。在從外部程序存儲(chǔ)器獲取和訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)，端口2排放高階地址字節(jié)，使用16位地址（MOVX @ DPTR）。在此應(yīng)用中，它使用了強(qiáng)大的內(nèi)部上拉發(fā)送1時(shí)。在訪問外部數(shù)據(jù)存儲(chǔ)器，使用8位地址，端口2發(fā)出的P2特殊功能寄存器的內(nèi)容。 P2口也接收高地址位在flash編程和校驗(yàn)和一些控制信號(hào)。
端口3：端口3是一個(gè)8位雙向I / O的端口內(nèi)部上拉UPS。端口3輸出緩沖器可以吸收/源四個(gè)TTL輸入。當(dāng)1寫入端口3他們拉高的內(nèi)部上拉，并可以用作輸入引腳。低將作為輸入，3口被外部拉低的引腳源電流（IIL）的上拉。 端口3也有軟下面列出的AT89C51的各種特殊功能的功能。
RST：復(fù)位輸入。該引腳上高一兩個(gè)機(jī)器周期，而振蕩器運(yùn)行的設(shè)備復(fù)位。
ALE / PROG：地址鎖存使輸出脈沖鎖存地址的低字節(jié)能訪問外部存儲(chǔ)器。該引腳也是方案在Flash編程脈沖輸入（PROG鍵）。在正常運(yùn)作的ALE發(fā)出恒定速率的1/6振蕩器頻率，可以使用外部時(shí)鐘或定時(shí)。但是請(qǐng)注意，這一個(gè)ALE脈沖被跳過，在每次訪問外部數(shù)據(jù)存儲(chǔ)器。如果需要，可以禁止ALE操作設(shè)置位 0 SFR的位置8EH。位設(shè)置，ALE僅在執(zhí)行MOVX或MOVC指令。否則，腳弱拉高。設(shè)置的ALE禁止位有沒有效果，如果微處理器在外部執(zhí)行模式。
PSEN：程序存儲(chǔ)是外部程序存儲(chǔ)器的讀選通，當(dāng)theAT89C51執(zhí)行代碼從外部程序存儲(chǔ)器時(shí)，除了兩個(gè)PSEN的激活在每次訪問外部數(shù)據(jù)存儲(chǔ)器跳過，PSEN是激活每個(gè)機(jī)器周期的兩倍。
EA / VPP：外部訪問啟用。 EA必須綁到GND為了使設(shè)備開始在0000H到FFFFH的外部程序存儲(chǔ)器位置獲取代碼。但是請(qǐng)注意，如果鎖定位1編程，EA將在內(nèi)部復(fù)位鎖存。 EA應(yīng)綁到VCC內(nèi)部程序執(zhí)行。此引腳的所接收12伏的編程電壓（VPP），需要12伏VPP的零件，使Flash編程期間。
芯片擦除：
通過適當(dāng)?shù)目刂菩盘?hào)組合，并通過控股的ALE / 10毫秒編低，電擦除整個(gè)Flash陣列。所有“1”寫的代碼陣列芯片擦除操作前必須執(zhí)行的代碼存儲(chǔ)器可以重新編程。
編程接口
閃存陣列中的每一個(gè)代碼的字節(jié)可以被寫入，并可以通過適當(dāng)?shù)目刂菩盘?hào)組合擦除整個(gè)陣列。操作周期是自定時(shí)，而且一旦啟動(dòng)，將由時(shí)間來自動(dòng)來完成。微機(jī)接口之間的信息轉(zhuǎn)換微機(jī)電子系統(tǒng)處理的信息外兩種形式。存在一個(gè)物理信號(hào)，但該計(jì)劃之內(nèi)，它代表的是數(shù)值。任何接口的功能可以分為以某種方式修改數(shù)據(jù)的操作的數(shù)量，這樣的內(nèi)部和外部的形式之間的轉(zhuǎn)換過程中進(jìn)行了一些步驟。模擬 - 數(shù)字轉(zhuǎn)換器，用于連續(xù)可變的信號(hào)轉(zhuǎn)換成相應(yīng)的數(shù)字形式，可采取的任何一個(gè)可能的固定的二進(jìn)制值。如果不是連續(xù)變化的傳感器的輸出，ADC是沒有必要的。在這種情況下，信號(hào)調(diào)理部分必須輸入信號(hào)轉(zhuǎn)換成一個(gè)可以直接連接到旁邊的接口部分的形式，微機(jī)本身的輸出接口輸入/輸出部分，采取了類似的形式，明顯的區(qū)別是，這里的信息是流在相反的方向，它是通過計(jì)劃從內(nèi)到外界，在這種情況下，該程序可能調(diào)用一個(gè)輸出子程序監(jiān)督操作界面和執(zhí)行的比例可用于數(shù)字 - 模擬轉(zhuǎn)換器所需的數(shù)字。這個(gè)子程序依次傳遞的信息，可以被轉(zhuǎn)換成相應(yīng)的電信號(hào)輸出設(shè)備使用DAC模擬形式。最后信號(hào)的條件適合的形式經(jīng)營(yíng)的執(zhí)行機(jī)構(gòu)。在微電腦電路所使用的信號(hào)幾乎總是太小，直接連接到外界，必須使用某種接口翻譯。接口電路部分的設(shè)計(jì)是我們已經(jīng)看到，找到更合適他們的一個(gè)形式，是在微型計(jì)算機(jī)的信息離散位模式表示有意申請(qǐng)微機(jī)的工程師面臨的最重要的任務(wù)之一，這個(gè)數(shù)字的形式是最有用的微機(jī)連接到設(shè)備只可以開啟或關(guān)閉，其中每個(gè)位代表一個(gè)開關(guān)或調(diào)??節(jié)器。為了解決現(xiàn)實(shí)世界問題的狀態(tài)，有時(shí)微控制器必須超過只是一個(gè)CPU，一個(gè)程序和數(shù)據(jù)存儲(chǔ)器。此外，它必須包含硬件允許CPU訪問來自外界的信息。一旦CPU收集信息和處理數(shù)據(jù)，還必須能夠應(yīng)對(duì)外界部分的某些的變化。
外設(shè)微控制器提供的最基本的形式是通用I70端口，每個(gè)I / O引腳可以作為輸入或輸出使用。每個(gè)引腳的功能是通過寄存器設(shè)置或清除相應(yīng)的位在相應(yīng)的決定數(shù)據(jù)方向。在程序的初始化階段，每個(gè)輸出引腳可驅(qū)動(dòng)所使用的CPU指令引腳可以被視為使用程序指令的CPU。某種類型的邏輯1或邏輯0。串行單位包括微控制器，讓CPU與外部設(shè)備進(jìn)行通信的串行格式，需要更少的I / O引腳進(jìn)行的通信功能，串行傳輸進(jìn)行同步或異步，這使得它更便宜，但速度較慢，而不是使用位并行格式。