《2012-2013-2《數(shù)字邏輯設(shè)計(jì)及應(yīng)用》期末考試題-A參考解答.doc》由會(huì)員分享，可在線閱讀，更多相關(guān)《2012-2013-2《數(shù)字邏輯設(shè)計(jì)及應(yīng)用》期末考試題-A參考解答.doc（7頁(yè)珍藏版）》請(qǐng)?jiān)谘b配圖網(wǎng)上搜索。

學(xué)院 姓名 學(xué)號(hào) 任課老師 考場(chǎng)教室__________選課號(hào)/座位號(hào) ………密………封………線………以………內(nèi)………答………題………無(wú)………效…… 電子科技大學(xué)2012 -2013學(xué)年第 二 學(xué)期期 末 考試 A 卷 課程名稱：_數(shù)字邏輯設(shè)計(jì)及應(yīng)用__ 考試形式： 閉卷 考試日期： 20 13 年 07 月 05 日 考試時(shí)長(zhǎng)：_120___分鐘 課程成績(jī)構(gòu)成：平時(shí) 30 %， 期中 30 %， 實(shí)驗(yàn) 0 %， 期末 40 % 本試卷試題由___七_(dá)_部分構(gòu)成，共__7___頁(yè)。 題號(hào) 一 二 三 四 五 六 七 八 九 十 合計(jì) 得分 得 分 I. Fill out your answers in the blanks (3’ X 10=30’) 1. If a 74x138 binary decoder has 110 on its inputs CBA, the active LOW output Y5 should be ( 1 or high ). 2. If the next state of the unused states are marked as “don’t-cares” when designing a finite state machine, this approach is called minimal ( cost ) approach. 3.The RCO_L of 4-bit counter 74x169 is ( 0 or low ) when counting to 0000 in decreasing order. 4. To design a "001010" serial sequence generator by shift registers, the shift register should need ( 4 ) bit at least. 5. One state transition equation is Q*=JQ’+K’Q. If we use T flip-flop with enable to complete the equation，the enable input of T flip-flop should have the function EN=( JQ’+KQ ). 6. A 4-bit Binary counter can have ( 16 ) normal states at most, 4-bit Johnson counter with no self-correction can have ( 8 ) normal states, 4-bit linear feedback shift-register (LFSR) counter with self-correction can have ( 16 ) normal states. 7. If we use a ROM, whose capacity is 16 4 bits, to construct a 4-bit binary code to gray code converter, when the address inputs are 1001, ( 1101 ) will be the output. 8. When the input is 10000000 of an 8 bit DAC, the corresponding output voltage is 2V. The output voltage is ( 3.98 ) V when the input is 11111111. 得 分 II. Please select the only one correct answer in the following questions.(2’ X 5=10’) 1. If a 74x85 magnitude comparator has ALTBIN=1, AGTBIN=0, AEQBIN=0, A3A2A1A0=1101, B3B2B1B0=0111 on its inputs, the outputs are ( D ). A) ALTBOUT=0, AEQBOUT=0, AGTBOUT=0 B) ALTBOUT=1, AEQBOUT=0, AGTBOUT=0 C) ALTBOUT=1, AEQBOUT=0, AGTBOUT=1 D) ALTBOUT=0, AEQBOUT=0, AGTBOUT=1 2. As shown in Figure 1, what would the outputs of the 4-bit adder 74x283 be ( B ) when A3A2A1A0=0100, B3B2B1B0=1110 and S/A=1. A) C4=1, S3S2S1S0=0010 B) C4=0, S3S2S1S0=0110 C) C4=0, S3S2S1S0=1010 D) C4=0, S3S2S1S0=1110 Figure 1 3. Which of the following statements is INCORRECT? ( A ) A) A D latch is edge triggered and it will follow the input as long as the control input C is active low. B) A D flip flop is edge triggered and its output will not change until the edge of the controlling CLK signal. C) An S-R latch may go into metastable state if both S and R are changing from 11 to 00 simultaneously. D) The pulse applying to any input of an S -R latch must meet the minimum pulse width requirement. 4. The capacity of a memory that has 13 bits address bus and can store 8 bits at each address is ( B ). A) 8192 B) 65536 C) 104 D) 256 5. Which state in Figure 2 is NOT ambiguous ( C ). A) A B) B C) C and D D) C Figure 2 得 分 III. Analyze the sequential-circuit as shown in Figure 3, D Flip-Flop with asynchronous preset and clear inputs. [15’] 1.Write out the excitation equations, transition equations and output equation. [5’] 2.Assume the initial state Q2Q1=00, complete the timing diagram for Q2 ,Q1 and Z. [10’] Figure 3 參考答案： 激勵(lì)方程: D1=Q2/，D2= Q1 轉(zhuǎn)移方程：Q1 *= D1=Q2/，Q2 *=D2= Q1 輸出方程：Z= (CLK+Q2)/ 參考評(píng)分標(biāo)準(zhǔn)： 1. 5個(gè)方程正確得5分；每錯(cuò)一個(gè)扣1分，扣完5分為止； 2. Q1、Q2、Z的波形邊沿判斷正確，得3分，錯(cuò)一個(gè)，扣1分，扣完3分為止；每個(gè)上升沿和下降沿各0.5分，錯(cuò)1處扣0.5分，扣完7分為止。 得 分 IV. Analyze the sequential-circuit as shown below, which contains two 74x163 4-bit binary counter. [15’] 1. Write out the logic expression LD_L for U1 and CLR_L for U2.[4’] 2. Assume the initial state is 310, write out the state sequence for the circuit. [8’] 3. Describe the modulus for the circuit. [3’] The function table for 74x163 Inputs Current state Next state Outputs CLR_L LD_L ENT ENP QD QC QB QA QD* QC* QB* QA* RCO 0 X X X X X X X 0 0 0 0 0 1 0 X X X X X X D C B A 0 1 1 0 X X X X X QD QC QB QA 0 1 1 X 0 X X X X QD QC QB QA 0 1 1 1 1 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1 1 0 0 1 1 0 1 0 0 0 1 1 1 1 …………. ………….. 0 1 1 1 1 1 1 1 1 0 0 0 0 1 參考評(píng)分標(biāo)準(zhǔn)： 1. LD_L=Q3/,CLR_L=(Q5Q4Q3)/ [4’] 2. 狀態(tài)序列：十六進(jìn)制數(shù)表示：03,…08,13,…18,23,…28,33,…38,03,…08 或十進(jìn)制數(shù)表示：3,…8,19,…24,35,…40,51,…56,3,…8[8’] 錯(cuò)1處扣1分，扣完為止。 3. m=24 [3’] 得 分 V. Design a sequence signal generator with self-correcting to generate a serial output sequence of 101100, using a 74x194 and a 74x151.[15’] 1. List the transition table .[4’] 2. Write out the canonical sum of feedback function LIN.[[4’] 3. Draw the circuit diagram.[7’] The function table for 74x194 Iutputs Next state Function S1 S0 QA* QB* QC* QD* 0 0 0 1 1 0 1 1 QA QB QC QD RIN QA QB QC QB QC QD LIN A B C D Hold Shift right Shift left Load 參考評(píng)分標(biāo)準(zhǔn)： 1. 轉(zhuǎn)移表正確4分，錯(cuò)1行扣0.5分。 2. 反饋函數(shù)正確LIN=D0=∑m(0,2,4,5) [4’] 3. 電路圖正確7分，錯(cuò)1處扣0.5分，扣完為止。 得 分 VI. Write out the state/output table for a Mealy machine that can detect the pattern 10101 or 10111 . The output Z=1 when the pattern is detected. Your model should also be able to detect overlapping sequences. (10’) State meaning S X 0 1 Initial state A A, 0 B, 0 Got 1 B C, 0 B, 0 Got 10 C A, 0 D, 0 Got 101 D E, 0 F, 0 Got 1010 E A, 0 D, 1 Got 1011 F C, 0 B, 1 S*, Z 評(píng)分標(biāo)準(zhǔn)： 1.狀態(tài)定義正確得3分；每錯(cuò)一處扣0.5分，扣完3分為止； 2.狀態(tài)轉(zhuǎn)移正確，得5分；每錯(cuò)一處扣0.5分，扣完5分為止； 3.輸出正確，得2分；每錯(cuò)一處扣0.5分，扣完2分為止。 得 分 VII. Design a code converter with 2421 code to 8421 code，using a 74x85, a 74x283 and some gates if needed. [10’] 參考評(píng)分標(biāo)準(zhǔn)： 1.74x85級(jí)聯(lián)輸入端連接正確2分，比較值正確3分，74x283的C0端連接正確1分； 2.74x85的A3~A0與74x283的A3~A0連接正確2分； 3.74x85與74x283中間連接的電路正2分。 第 7 頁(yè) 共 7 頁(yè)